src/mainboard/purism/librem_skl/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # IGD Displays
   4         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
   5
   6         register "panel_cfg" = "{
   7                 .up_delay_ms            = 200,
   8                 .down_delay_ms          =  50,
   9                 .cycle_delay_ms         = 500,
  10                 .backlight_on_delay_ms  =   1,
  11                 .backlight_off_delay_ms = 200,
  12                 .backlight_pwm_hz       = 200,
  13         }"
  14
  15         register "deep_s3_enable_ac" = "0"
  16         register "deep_s3_enable_dc" = "0"
  17         register "deep_s5_enable_ac" = "0"
  18         register "deep_s5_enable_dc" = "0"
  19         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
  20
  21         register "eist_enable" = "true"
  22
  23         # Set the Thermal Control Circuit (TCC) activaction value to 95C
  24         # even though FSP integration guide says to set it to 100C for SKL-U
  25         # (offset at 0), because when the TCC activates at 100C, the CPU
  26         # will have already shut itself down from overheating protection.
  27         register "tcc_offset" = "5" # TCC of 95C
  28
  29         # GPE configuration
  30         # Note that GPE events called out in ASL code rely on this
  31         # route. i.e. If this route changes then the affected GPE
  32         # offset bits also need to be changed.
  33         register "gpe0_dw0" = "GPP_C"
  34         register "gpe0_dw1" = "GPP_D"
  35         register "gpe0_dw2" = "GPP_E"
  36
  37         # Disable DPTF
  38         register "dptf_enable" = "0"
  39
  40         # FSP Configuration
  41         register "DspEnable" = "0"
  42         register "IoBufferOwnership" = "0"
  43         register "SkipExtGfxScan" = "1"
  44         register "SaGv" = "SaGv_Enabled"
  45         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  46         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  47         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  48         register "PmConfigSlpAMinAssert" = "3"          # 2s
  49
  50         # VR Settings Configuration for 4 Domains
  51         #+----------------+-----------+-----------+-------------+----------+
  52         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  53         #+----------------+-----------+-----------+-------------+----------+
  54         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  55         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  56         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  57         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  58         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  59         #| ImonSlope      | 0         | 0         | 0           | 0        |
  60         #| ImonOffset     | 0         | 0         | 0           | 0        |
  61         #| IccMax         | 7A        | 34A       | 35A         | 35A      |
  62         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  63         #| AC LoadLine    | 15 mOhm   | 5.7 mOhm  | 5.2 mOhm    | 5.2 mOhm |
  64         #| DC LoadLine    | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm    | 4.2 mOhm |
  65         #+----------------+-----------+-----------+-------------+----------+
  66         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  67                 .vr_config_enable = 1,
  68                 .psi1threshold = VR_CFG_AMP(20),
  69                 .psi2threshold = VR_CFG_AMP(4),
  70                 .psi3threshold = VR_CFG_AMP(1),
  71                 .psi3enable = 1,
  72                 .psi4enable = 1,
  73                 .imon_slope = 0x0,
  74                 .imon_offset = 0x0,
  75                 .icc_max = VR_CFG_AMP(7),
  76                 .voltage_limit = 1520,
  77                 .ac_loadline = 1500,
  78                 .dc_loadline = 1430,
  79         }"
  80
  81         register "domain_vr_config[VR_IA_CORE]" = "{
  82                 .vr_config_enable = 1,
  83                 .psi1threshold = VR_CFG_AMP(20),
  84                 .psi2threshold = VR_CFG_AMP(5),
  85                 .psi3threshold = VR_CFG_AMP(1),
  86                 .psi3enable = 1,
  87                 .psi4enable = 1,
  88                 .imon_slope = 0x0,
  89                 .imon_offset = 0x0,
  90                 .icc_max = VR_CFG_AMP(34),
  91                 .voltage_limit = 1520,
  92                 .ac_loadline = 570,
  93                 .dc_loadline = 483,
  94         }"
  95
  96         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  97                 .vr_config_enable = 1,
  98                 .psi1threshold = VR_CFG_AMP(20),
  99                 .psi2threshold = VR_CFG_AMP(5),
 100                 .psi3threshold = VR_CFG_AMP(1),
 101                 .psi3enable = 1,
 102                 .psi4enable = 1,
 103                 .imon_slope = 0x0,
 104                 .imon_offset = 0x0,
 105                 .icc_max = VR_CFG_AMP(35),
 106                 .voltage_limit = 1520,
 107                 .ac_loadline = 520,
 108                 .dc_loadline = 420,
 109         }"
 110
 111         register "domain_vr_config[VR_GT_SLICED]" = "{
 112                 .vr_config_enable = 1,
 113                 .psi1threshold = VR_CFG_AMP(20),
 114                 .psi2threshold = VR_CFG_AMP(5),
 115                 .psi3threshold = VR_CFG_AMP(1),
 116                 .psi3enable = 1,
 117                 .psi4enable = 1,
 118                 .imon_slope = 0x0,
 119                 .imon_offset = 0x0,
 120                 .icc_max = VR_CFG_AMP(35),
 121                 .voltage_limit = 1520,
 122                 .ac_loadline = 520,
 123                 .dc_loadline = 420,
 124         }"
 125
 126         # PL2 override 25W
 127         register "power_limits_config" = "{
 128                 .tdp_pl2_override = 25,
 129         }"
 130
 131         # Send an extra VR mailbox command for the PS4 exit issue
 132         register "SendVrMbxCmd" = "2"
 133
 134         device domain 0 on
 135                 device ref igpu         on  end
 136                 device ref sa_thermal   on  end
 137                 device ref south_xhci   on  end
 138                 device ref south_xdci   on  end
 139                 device ref thermal      on  end
 140                 device ref sata         on
 141                         register "SataPortsEnable" = "{
 142                                 [0] = 1,
 143                                 [2] = 1,
 144                         }"
 145                 end
 146                 device ref pcie_rp5     on
 147                         register "PcieRpEnable[4]" = "1"
 148                 end
 149                 device ref pcie_rp9     on
 150                         register "PcieRpEnable[8]" = "1"
 151                 end
 152                 device ref lpc_espi     on
 153                         # EC/KBC requires continuous mode
 154                         register "serirq_mode" = "SERIRQ_CONTINUOUS"
 155
 156                         # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
 157                         register "gen1_dec" = "0x00000381"
 158                         chip drivers/pc80/tpm
 159                                 device pnp 0c31.0 on end
 160                         end
 161                 end
 162                 device ref hda          on  end
 163                 device ref smbus        on  end
 164                 device ref fast_spi     on  end
 165         end
 166 end