src/mainboard/ti/beaglebone/ddr3.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Parameters to initialise the DDR3 memory on the Beaglebone Black
   5  * Taken and adapted from U-Boot.
   6  */
   7
   8 #ifndef __MAINBOARD_TI_BEAGLEBONE_DDR3_H__
   9 #define __MAINBOARD_TI_BEAGLEBONE_DDR3_H__
  10
  11 /* Micron MT41K256M16HA-125E */
  12 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
  13 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
  14 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
  15 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
  16 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
  17 #define MT41K256M16HA125E_EMIF_SDREF 0xC30
  18 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
  19 #define MT41K256M16HA125E_RATIO 0x80
  20 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0
  21 #define MT41K256M16HA125E_RD_DQS 0x38
  22 #define MT41K256M16HA125E_WR_DQS 0x44
  23 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D
  24 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
  25 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
  26
  27 #define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
  28
  29 #endif