src/southbridge/intel/bd82x6x/early_me.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <device/pci_ops.h>
   5 #include <cf9_reset.h>
   6 #include <console/console.h>
   7 #include <delay.h>
   8 #include <device/pci_def.h>
   9 #include <halt.h>
  10 #include <southbridge/intel/common/me.h>
  11 #include <timestamp.h>
  12 #include "me.h"
  13 #include "pch.h"
  14
  15 static const char *me_ack_values[] = {
  16         [ME_HFS_ACK_NO_DID]     = "No DID Ack received",
  17         [ME_HFS_ACK_RESET]      = "Non-power cycle reset",
  18         [ME_HFS_ACK_PWR_CYCLE]  = "Power cycle reset",
  19         [ME_HFS_ACK_S3]         = "Go to S3",
  20         [ME_HFS_ACK_S4]         = "Go to S4",
  21         [ME_HFS_ACK_S5]         = "Go to S5",
  22         [ME_HFS_ACK_GBL_RESET]  = "Global Reset",
  23         [ME_HFS_ACK_CONTINUE]   = "Continue to boot"
  24 };
  25
  26 void intel_early_me_status(void)
  27 {
  28         union me_hfs hfs;
  29         union me_gmes gmes;
  30         u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
  31
  32         if ((id == 0xffffffff) || (id == 0x00000000) ||
  33             (id == 0x0000ffff) || (id == 0xffff0000)) {
  34                 printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n");
  35         } else {
  36                 hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
  37                 gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
  38
  39                 intel_me_status(&hfs, &gmes);
  40         }
  41 }
  42
  43 int intel_early_me_init(void)
  44 {
  45         int count;
  46         union me_uma uma;
  47         union me_hfs hfs;
  48
  49         printk(BIOS_INFO, "Intel ME early init\n");
  50
  51         /* Wait for ME UMA SIZE VALID bit to be set */
  52         for (count = ME_RETRY; count > 0; --count) {
  53                 uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
  54                 if (uma.valid)
  55                         break;
  56                 udelay(ME_DELAY);
  57         }
  58         if (!count) {
  59                 printk(BIOS_ERR, "ME is not ready!\n");
  60                 return -1;
  61         }
  62
  63         /* Check for valid firmware */
  64         hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
  65         if (hfs.fpt_bad) {
  66                 printk(BIOS_WARNING, "ME has bad firmware\n");
  67                 return -1;
  68         }
  69
  70         printk(BIOS_INFO, "Intel ME firmware is ready\n");
  71         return 0;
  72 }
  73
  74 int intel_early_me_uma_size(void)
  75 {
  76         union me_uma uma;
  77
  78         uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
  79         if (uma.valid) {
  80                 printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
  81                 return uma.size;
  82         }
  83
  84         printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
  85         return 0;
  86 }
  87
  88 int intel_early_me_init_done(u8 status)
  89 {
  90         u8 reset, errorcode, opmode;
  91         u32 mebase_l, mebase_h;
  92         u32 millisec;
  93         u32 hfs, me_fws2;
  94         union me_did did = {
  95                 .init_done = ME_INIT_DONE,
  96                 .status = status
  97         };
  98         u32 meDID;
  99
 100         hfs = (pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) & 0xff000) >> 12;
 101
 102         opmode = (hfs & 0xf0) >> 4;
 103         errorcode = hfs & 0xf;
 104
 105         if (opmode != ME_HFS_MODE_NORMAL) {
 106                 printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
 107                 //return 0;
 108         }
 109         if (errorcode) {
 110                 printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
 111                 //return 0;
 112         }
 113
 114         me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
 115         printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
 116         printk(BIOS_NOTICE, "ME:  Bist in progress: 0x%x\n", me_fws2 & 0x1);
 117         printk(BIOS_NOTICE, "ME:  ICC Status      : 0x%x\n", (me_fws2 & 0x6) >> 1);
 118         printk(BIOS_NOTICE, "ME:  Invoke MEBx     : 0x%x\n", (me_fws2 & 0x8) >> 3);
 119         printk(BIOS_NOTICE, "ME:  CPU replaced    : 0x%x\n", (me_fws2 & 0x10) >> 4);
 120         printk(BIOS_NOTICE, "ME:  MBP ready       : 0x%x\n", (me_fws2 & 0x20) >> 5);
 121         printk(BIOS_NOTICE, "ME:  MFS failure     : 0x%x\n", (me_fws2 & 0x40) >> 6);
 122         printk(BIOS_NOTICE, "ME:  Warm reset req  : 0x%x\n", (me_fws2 & 0x80) >> 7);
 123         printk(BIOS_NOTICE, "ME:  CPU repl valid  : 0x%x\n", (me_fws2 & 0x100) >> 8);
 124         printk(BIOS_NOTICE, "ME:  (Reserved)      : 0x%x\n", (me_fws2 & 0x600) >> 9);
 125         printk(BIOS_NOTICE, "ME:  FW update req   : 0x%x\n", (me_fws2 & 0x800) >> 11);
 126         printk(BIOS_NOTICE, "ME:  (Reserved)      : 0x%x\n", (me_fws2 & 0xf000) >> 12);
 127         printk(BIOS_NOTICE, "ME:  Current state   : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
 128         printk(BIOS_NOTICE, "ME:  Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
 129         printk(BIOS_NOTICE, "ME:  Progress code   : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
 130
 131         /* Poll CPU replaced for 50ms */
 132         millisec = 0;
 133         while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
 134                 udelay(1000);
 135                 me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
 136                 millisec++;
 137         }
 138         if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
 139                 printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
 140         } else if ((me_fws2 & 0x100) == 0x100) {
 141                 if ((me_fws2 & 0x80) == 0x80) {
 142                         printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
 143                         pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~0x80);
 144                         set_global_reset(0);
 145                         system_reset();
 146                 }
 147
 148                 if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
 149                         printk(BIOS_NOTICE, "Full training required\n");
 150                 }
 151         }
 152
 153         printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
 154
 155         /* MEBASE from MESEG_BASE[35:20] */
 156         mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
 157         mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
 158         did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
 159
 160         meDID = did.uma_base | (1 << 28);// | (1 << 23);
 161         pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, meDID);
 162
 163         /* Must wait for ME acknowledgement */
 164         if (opmode == ME_HFS_MODE_DEBUG) {
 165                 printk(BIOS_NOTICE,
 166                         "ME: ME is reporting as disabled, "
 167                         "so not waiting for a response.\n");
 168         } else {
 169                 timestamp_add_now(TS_ME_INFORM_DRAM_START);
 170                 udelay(100);
 171                 millisec = 0;
 172                 do {
 173                         udelay(1000);
 174                         hfs = (pci_read_config32(
 175                                 PCH_ME_DEV, PCI_ME_HFS) & 0xfe000000)
 176                                 >> 24;
 177                         millisec++;
 178                 } while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
 179                         && (millisec <= 5000));
 180                 timestamp_add_now(TS_ME_INFORM_DRAM_END);
 181         }
 182
 183         me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
 184         printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
 185         printk(BIOS_NOTICE, "ME:  Bist in progress: 0x%x\n", me_fws2 & 0x1);
 186         printk(BIOS_NOTICE, "ME:  ICC Status      : 0x%x\n", (me_fws2 & 0x6) >> 1);
 187         printk(BIOS_NOTICE, "ME:  Invoke MEBx     : 0x%x\n", (me_fws2 & 0x8) >> 3);
 188         printk(BIOS_NOTICE, "ME:  CPU replaced    : 0x%x\n", (me_fws2 & 0x10) >> 4);
 189         printk(BIOS_NOTICE, "ME:  MBP ready       : 0x%x\n", (me_fws2 & 0x20) >> 5);
 190         printk(BIOS_NOTICE, "ME:  MFS failure     : 0x%x\n", (me_fws2 & 0x40) >> 6);
 191         printk(BIOS_NOTICE, "ME:  Warm reset req  : 0x%x\n", (me_fws2 & 0x80) >> 7);
 192         printk(BIOS_NOTICE, "ME:  CPU repl valid  : 0x%x\n", (me_fws2 & 0x100) >> 8);
 193         printk(BIOS_NOTICE, "ME:  (Reserved)      : 0x%x\n", (me_fws2 & 0x600) >> 9);
 194         printk(BIOS_NOTICE, "ME:  FW update req   : 0x%x\n", (me_fws2 & 0x800) >> 11);
 195         printk(BIOS_NOTICE, "ME:  (Reserved)      : 0x%x\n", (me_fws2 & 0xf000) >> 12);
 196         printk(BIOS_NOTICE, "ME:  Current state   : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
 197         printk(BIOS_NOTICE, "ME:  Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
 198         printk(BIOS_NOTICE, "ME:  Progress code   : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
 199
 200         /* Return the requested BIOS action */
 201         printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
 202                 me_ack_values[(hfs & 0xe) >> 1]);
 203
 204         reset = inb(0xcf9);
 205         reset &= 0xf1;
 206         switch ((hfs & 0xe) >> 1) {
 207         case ME_HFS_ACK_NO_DID:
 208         case ME_HFS_ACK_CONTINUE:
 209                 /* Continue to boot */
 210                 return 0;
 211         case ME_HFS_ACK_RESET:
 212                 /* Non-power cycle reset */
 213                 set_global_reset(0);
 214                 reset |= 0x06;
 215                 break;
 216         case ME_HFS_ACK_PWR_CYCLE:
 217                 /* Power cycle reset */
 218                 set_global_reset(0);
 219                 reset |= 0x0e;
 220                 break;
 221         case ME_HFS_ACK_GBL_RESET:
 222                 /* Global reset */
 223                 set_global_reset(1);
 224                 reset |= 0x0e;
 225                 break;
 226         case ME_HFS_ACK_S3:
 227         case ME_HFS_ACK_S4:
 228         case ME_HFS_ACK_S5:
 229                 break;
 230         }
 231
 232         /* Perform the requested reset */
 233         if (reset) {
 234                 outb(reset, 0xcf9);
 235                 halt();
 236         }
 237         return -1;
 238 }