src/southbridge/intel/bd82x6x/early_pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <cf9_reset.h>
   6 #include <device/pci_def.h>
   7 #include <device/smbus_host.h>
   8 #include <southbridge/intel/common/gpio.h>
   9 #include <southbridge/intel/common/pmbase.h>
  10 #include <southbridge/intel/common/rcba.h>
  11
  12 /* For DMI bar.  */
  13 #include <northbridge/intel/sandybridge/sandybridge.h>
  14
  15 #include "pch.h"
  16 #include "chip.h"
  17
  18 #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
  19 #define PCI_DEVICE_ID_INTEL_UM77 0x1e58
  20
  21 static void wait_iobp(void)
  22 {
  23         while (RCBA8(IOBPS) & 1)
  24                 ; // implement timeout?
  25 }
  26
  27 static u32 read_iobp(u32 address)
  28 {
  29         u32 ret;
  30
  31         RCBA32(IOBPIRI) = address;
  32         RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
  33         wait_iobp();
  34         ret = RCBA32(IOBPD);
  35         wait_iobp();
  36         RCBA8(IOBPS); // call wait_iobp() instead here?
  37         return ret;
  38 }
  39
  40 static void write_iobp(u32 address, u32 val)
  41 {
  42         /* this function was probably pch_iobp_update with the andvalue
  43          * being 0. So either the IOBP read can be removed or this function
  44          * and the pch_iobp_update function in ramstage could be merged */
  45         read_iobp(address);
  46         RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
  47         wait_iobp();
  48
  49         RCBA32(IOBPD) = val;
  50         wait_iobp();
  51         RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
  52
  53         RCBA8(IOBPS); // call wait_iobp() instead here?
  54 }
  55
  56 void early_pch_init_native_dmi_pre(void)
  57 {
  58         /* Link Capabilities Register */
  59         RCBA32(LCAP) = (RCBA32(LCAP) & ~0x3fc00) |
  60                          (3 << 10) | // L0s and L1 entry supported
  61                          (2 << 12) | // L0s 128 ns to less than 256 ns
  62                          (2 << 15);  // L1 2 us to less than 4 us
  63
  64         RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16);
  65         RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2;
  66 }
  67
  68 void early_pch_init_native_dmi_post(void)
  69 {
  70         RCBA32(CIR0);   // !!! = 0x01200654
  71         RCBA32(CIR0) = 0x01200654;
  72         RCBA32(CIR0);   // !!! = 0x01200654
  73         RCBA32(CIR0) = 0x012a0654;
  74         RCBA32(CIR0);   // !!! = 0x012a0654
  75         RCBA8(UPDCR);   // !!! = 0x00
  76         RCBA8(UPDCR) = 0x05;
  77
  78         /*
  79          * Virtual Channel resources must match settings in DMIBAR!
  80          *
  81          * Some of the following settings are taken from
  82          * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel
  83          * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and
  84          * serialice traces.
  85          */
  86
  87         /* Virtual Channel 0 Resource Control Register.
  88          * Enable channel.
  89          * Set Virtual Channel Identifier.
  90          * Map TC0 and TC3 and TC4 to VC0.
  91          */
  92
  93         RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
  94
  95         /* Virtual Channel 1 Resource Control Register.
  96          * Enable channel.
  97          * Set Virtual Channel Identifier.
  98          * Map TC1 and TC5 to VC1.
  99          */
 100         RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1);
 101         /* Read back register */
 102         RCBA32(V1CTL);
 103
 104         /* Virtual Channel private Resource Control Register.
 105          * Enable channel.
 106          * Set Virtual Channel Identifier.
 107          * Map TC2 and TC6 to VCp.
 108          */
 109         RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1);
 110         /* Read back register */
 111         RCBA32(CIR31);
 112
 113         /* Virtual Channel ME Resource Control Register.
 114          * Enable channel.
 115          * Set Virtual Channel Identifier.
 116          * Map TC7 to VCm.
 117          */
 118         RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1);
 119
 120         /* Lock Virtual Channel Resource control register. */
 121         RCBA32(CIR0) |= TCLOCKDN;
 122         /* Read back register */
 123         RCBA32(CIR0);
 124
 125         /* Wait for virtual channels negotiation pending */
 126         while (RCBA16(V0STS) & VCNEGPND)
 127                 ;
 128         while (RCBA16(V1STS) & VCNEGPND)
 129                 ;
 130         while (RCBA16(0x2036) & VCNEGPND)
 131                 ;
 132         while (RCBA16(0x2046) & VCNEGPND)
 133                 ;
 134 }
 135
 136 void early_pch_init_native(void)
 137 {
 138         const u16 dev_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
 139         u8 pcie_ports = (dev_id == PCI_DEVICE_ID_INTEL_UM77) ? 4 : 8;
 140
 141         pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
 142
 143         /* Clear this bit early for PCIe device detection */
 144         for (uint8_t i = 0; i < pcie_ports; i++)
 145                 pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0);
 146
 147         RCBA32(CIR1) = 0x00109000;
 148         RCBA32(REC); // !!! = 0x00000000
 149         RCBA32(REC) = 0x40000000;
 150         RCBA32(0x100c) = 0x01110000;
 151         RCBA8(0x2340) = 0x1b;
 152         RCBA32(CIR6); // !!! = 0x0a080000
 153         RCBA32(CIR6) = 0x0a280000;
 154         RCBA32(0x2310); // !!! = 0xc809605b
 155         RCBA32(0x2310) = 0xa809605b;
 156         RCBA32(DMC2) = 0x00854c74;
 157         RCBA8(RPC);  // !!! = 0x00
 158         RCBA32(0x2310); // !!! = 0xa809605b
 159         RCBA32(0x2310) = 0xa809605b;
 160         RCBA32(0x2310); // !!! = 0xa809605b
 161         RCBA32(0x2310) = 0xa809605b;
 162
 163         write_iobp(0xea007f62, 0x00590133);
 164         write_iobp(0xec007f62, 0x00590133);
 165         write_iobp(0xec007f64, 0x59555588);
 166         write_iobp(0xea0040b9, 0x0001051c);
 167         write_iobp(0xeb0040a1, 0x800084ff);
 168         write_iobp(0xec0040a1, 0x800084ff);
 169         write_iobp(0xea004001, 0x00008400);
 170         write_iobp(0xeb004002, 0x40201758);
 171         write_iobp(0xec004002, 0x40201758);
 172         write_iobp(0xea004002, 0x00601758);
 173         write_iobp(0xea0040a1, 0x810084ff);
 174         write_iobp(0xeb0040b1, 0x0001c598);
 175         write_iobp(0xec0040b1, 0x0001c598);
 176         write_iobp(0xeb0040b6, 0x0001c598);
 177         write_iobp(0xea0000a9, 0x80ff969f);
 178         write_iobp(0xea0001a9, 0x80ff969f);
 179         write_iobp(0xeb0040b2, 0x0001c396);
 180         write_iobp(0xeb0040b3, 0x0001c396);
 181         write_iobp(0xec0040b2, 0x0001c396);
 182         write_iobp(0xea0001a9, 0x80ff94ff);
 183         write_iobp(SATA_IOBP_SP0G3IR, 0x0088037f);
 184         write_iobp(0xea0000a9, 0x80ff94ff);
 185         write_iobp(SATA_IOBP_SP1G3IR, 0x0088037f);
 186
 187         write_iobp(0xea007f05, 0x00010642);
 188         write_iobp(0xea0040b7, 0x0001c91c);
 189         write_iobp(0xea0040b8, 0x0001c91c);
 190         write_iobp(0xeb0040a1, 0x820084ff);
 191         write_iobp(0xec0040a1, 0x820084ff);
 192         write_iobp(0xea007f0a, 0xc2480000);
 193
 194         write_iobp(0xec00404d, 0x1ff177f);
 195         write_iobp(0xec000084, 0x5a600000);
 196         write_iobp(0xec000184, 0x5a600000);
 197         write_iobp(0xec000284, 0x5a600000);
 198         write_iobp(0xec000384, 0x5a600000);
 199         write_iobp(0xec000094, 0x000f0501);
 200         write_iobp(0xec000194, 0x000f0501);
 201         write_iobp(0xec000294, 0x000f0501);
 202         write_iobp(0xec000394, 0x000f0501);
 203         write_iobp(0xec000096, 0x00000001);
 204         write_iobp(0xec000196, 0x00000001);
 205         write_iobp(0xec000296, 0x00000001);
 206         write_iobp(0xec000396, 0x00000001);
 207         write_iobp(0xec000001, 0x00008c08);
 208         write_iobp(0xec000101, 0x00008c08);
 209         write_iobp(0xec000201, 0x00008c08);
 210         write_iobp(0xec000301, 0x00008c08);
 211         write_iobp(0xec0040b5, 0x0001c518);
 212         write_iobp(0xec000087, 0x06077597);
 213         write_iobp(0xec000187, 0x06077597);
 214         write_iobp(0xec000287, 0x06077597);
 215         write_iobp(0xec000387, 0x06077597);
 216         write_iobp(0xea000050, 0x00bb0157);
 217         write_iobp(0xea000150, 0x00bb0157);
 218         write_iobp(0xec007f60, 0x77777d77);
 219         write_iobp(0xea00008d, 0x01320000);
 220         write_iobp(0xea00018d, 0x01320000);
 221         write_iobp(0xec0007b2, 0x04514b5e);
 222         write_iobp(0xec00078c, 0x40000200);
 223         write_iobp(0xec000780, 0x02000020);
 224 }
 225
 226 static void pch_enable_bars(void)
 227 {
 228         pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
 229
 230         pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
 231
 232         pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
 233
 234         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
 235
 236         /* Enable GPIO functionality. */
 237         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 238 }
 239
 240 static void pch_generic_setup(void)
 241 {
 242         RCBA32(GCS) = RCBA32(GCS) | (1 << 5);   /* No reset */
 243         write_pmbase16(TCO1_CNT, 1 << 11);      /* halt timer */
 244 }
 245
 246 static void pch_enable_gbe(void)
 247 {
 248         uint8_t wanted_buc;
 249
 250         /* Don't do this in the bootblock, it might be RO. So one
 251            couldn't change the setting later in an updated romstage. */
 252         if (ENV_BOOTBLOCK)
 253                 return;
 254
 255         const struct device *const gbe = pcidev_on_root(0x19, 0);
 256         if (gbe && gbe->enabled)
 257                 wanted_buc = RCBA8(BUC) & ~PCH_DISABLE_GBE;
 258         else
 259                 wanted_buc = RCBA8(BUC) | PCH_DISABLE_GBE;
 260
 261         if (RCBA8(BUC) != wanted_buc) {
 262                 RCBA8(BUC) = wanted_buc;
 263                 /* Be double sure not to reset for naught. */
 264                 if (RCBA8(BUC) != wanted_buc)
 265                         return;
 266                 full_reset();
 267         }
 268 }
 269
 270 static void pch_enable_lpc_decode(void)
 271 {
 272         /*
 273          * Enable some common LPC IO ranges:
 274          * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
 275          * - 0x60/0x64, 0x62/0x66 often KBC/EC
 276          * - 0x3f0-0x3f5/0x3f7 FDD
 277          * - 0x378-0x37f and 0x778-0x77f LPT
 278          * - 0x2f8-0x2ff COMB
 279          * - 0x3f8-0x3ff COMA
 280          */
 281         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
 282         pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN
 283                 | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
 284
 285         const struct device *dev = pcidev_on_root(0x1f, 0);
 286         const struct southbridge_intel_bd82x6x_config *config = NULL;
 287
 288         /* Set up generic decode ranges */
 289         if (!dev)
 290                 return;
 291         if (dev->chip_info)
 292                 config = dev->chip_info;
 293         if (!config)
 294                 return;
 295
 296         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
 297         pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
 298         pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
 299         pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 300 }
 301
 302 __weak void mainboard_pch_lpc_setup(void)
 303 {
 304 }
 305
 306 void early_pch_init(void)
 307 {
 308         pch_enable_lpc_decode();
 309
 310         mainboard_pch_lpc_setup();
 311
 312         pch_enable_bars();
 313
 314         pch_generic_setup();
 315
 316         pch_enable_gbe();
 317
 318         setup_pch_gpios(&mainboard_gpio_map);
 319
 320         if (ENV_RAMINIT || (CONFIG(CONSOLE_I2C_SMBUS) && ENV_INITIAL_STAGE))
 321                 enable_smbus();
 322 }