src/southbridge/intel/bd82x6x/usb_xhci.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include "pch.h"
   8 #include <device/pci_ehci.h>
   9 #include <device/pci_ops.h>
  10 #include "chip.h"
  11
  12 static void usb_xhci_init(struct device *dev)
  13 {
  14         u32 reg32;
  15         struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
  16
  17         printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
  18
  19         if (config->xhci_overcurrent_mapping)
  20                 pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
  21
  22         /* lock overcurrent map */
  23         pci_or_config32(dev, 0x44, 1);
  24
  25         pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports);
  26         pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports);
  27
  28         /* Enable clock gating */
  29         reg32 = pci_read_config32(dev, 0x40);
  30         reg32 &= ~((1 << 20) | (1 << 21));
  31         reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
  32         reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
  33         reg32 |= (1 << 31); /* lock */
  34         pci_write_config32(dev, 0x40, reg32);
  35
  36         printk(BIOS_DEBUG, "done.\n");
  37 }
  38
  39 static const char *xhci_acpi_name(const struct device *dev)
  40 {
  41         return "XHC";
  42 }
  43
  44 struct device_operations bd82x6x_usb_xhci_ops = {
  45         .read_resources         = pci_dev_read_resources,
  46         .set_resources          = pci_dev_set_resources,
  47         .enable_resources       = pci_dev_enable_resources,
  48         .init                   = usb_xhci_init,
  49         .ops_pci                = &pci_dev_ops_pci,
  50         .acpi_name              = xhci_acpi_name,
  51 };