?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
soc/intel/xeon_sp: Drop uncore_fill_ssdt
[coreboot2.git] / util / amdfwtool / amdfwtool.c
blobef97010829ad518ec27558c07827562179fd8fab
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * ROMSIG At ROMBASE + 0x[0,2,4,8]20000:
5 * 0 4 8 C
6 * +------------+---------------+----------------+------------+
7 * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
8 * +------------+---------------+----------------+------------+
9 * | PSPDIR ADDR|PSPDIR ADDR(C) | BDT ADDR 0 | BDT ADDR 1 |
10 * +------------+---------------+----------------+------------+
11 * | BDT ADDR 2 | | BDT ADDR 3(C) | |
12 * +------------+---------------+----------------+------------+
13 * (C): Could be a combo header
14 *
15 * EC ROM should be 64K aligned.
16 *
17 * PSP directory (Where "PSPDIR ADDR" points)
18 * +------------+---------------+----------------+------------+
19 * | 'PSP$' | Fletcher | Count | Reserved |
20 * +------------+---------------+----------------+------------+
21 * | 0 | size | Base address | Reserved | Pubkey
22 * +------------+---------------+----------------+------------+
23 * | 1 | size | Base address | Reserved | Bootloader
24 * +------------+---------------+----------------+------------+
25 * | 8 | size | Base address | Reserved | Smu Firmware
26 * +------------+---------------+----------------+------------+
27 * | 3 | size | Base address | Reserved | Recovery Firmware
28 * +------------+---------------+----------------+------------+
29 * | |
30 * | |
31 * | Other PSP Firmware |
32 * | |
33 * +------------+---------------+----------------+------------+
34 * | 40 | size | Base address | Reserved |---+
35 * +------------+---------------+----------------+------------+ |
36 * :or 48(A/B A): size : Base address : Reserved : |
37 * + - - + - - + - - + - - + |
38 * : 4A(A/B B): size : Base address : Reserved : |
39 * +------------+---------------+----------------+------------+ |
40 * (A/B A) & (A/B B): Similar as 40, pointing to PSP level 2 |
41 * for A/B recovery |
42 * |
43 * |
44 * +------------+---------------+----------------+------------+ |
45 * | '2LP$' | Fletcher | Count | Reserved |<--+
46 * +------------+---------------+----------------+------------+
47 * | |
48 * | |
49 * | PSP Firmware |
50 * | (2nd-level is not required on all families) |
51 * | |
52 * +------------+---------------+----------------+------------+
53 * BIOS Directory Table (BDT) is similar
54 *
55 * PSP Combo directory
56 * +------------+---------------+----------------+------------+
57 * | 'PSP2' | Fletcher | Count |Look up mode|
58 * +------------+---------------+----------------+------------+
59 * | R e s e r v e d |
60 * +------------+---------------+----------------+------------+
61 * | ID-Sel | PSP ID | PSPDIR ADDR | | 1st PSP directory
62 * +------------+---------------+----------------+------------+
63 * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory
64 * +------------+---------------+----------------+------------+
65 * | |
66 * | Other PSP |
67 * | |
68 * +------------+---------------+----------------+------------+
69 * BDT Combo is similar
70 */
71
72 #include <commonlib/bsd/helpers.h>
73 #include <fcntl.h>
74 #include <errno.h>
75 #include <limits.h>
76 #include <stdbool.h>
77 #include <stdio.h>
78 #include <sys/stat.h>
79 #include <sys/types.h>
80 #include <unistd.h>
81 #include <string.h>
82 #include <stdlib.h>
83 #include <libgen.h>
84 #include <stdint.h>
85
86 #include "amdfwtool.h"
87
88 #define AMD_ROMSIG_OFFSET 0x20000
89
90 #define _MAX(A, B) (((A) > (B)) ? (A) : (B))
91
92 static void output_manifest(int manifest_fd, amd_fw_entry *fw_entry);
93
94 /*
95 * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP
96 * can support an optional "combo" implementation. If the PSP sees the
97 * PSP2 cookie, it interprets the table as a roadmap to additional PSP
98 * tables. Using this, support for multiple product generations may be
99 * built into one image. If the PSP$ cookie is found, the table is a
100 * normal directory table.
101 *
102 * Modern generations supporting the combo directories require the
103 * pointer to be at offset 0x14 of the Embedded Firmware Structure,
104 * regardless of the type of directory used. The --use-combo
105 * argument enforces this placement.
106 *
107 * TODO: Future work may require fully implementing the PSP_COMBO feature.
108 */
109
110 /*
111 * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
112 * The checksum field of the passed PDU does not need to be reset to zero.
113 *
114 * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
115 * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
116 * alternative to cyclical redundancy checks because it provides error-
117 * detection properties similar to cyclical redundancy checks but at the
118 * cost of a simple summation technique. Its characteristics were first
119 * published in IEEE Transactions on Communications in January 1982. One
120 * version has been adopted by ISO for use in the class-4 transport layer
121 * of the network protocol.
122 *
123 * This program expects:
124 * stdin: The input file to compute a checksum for. The input file
125 * not be longer than 256 bytes.
126 * stdout: Copied from the input file with the Fletcher's Checksum
127 * inserted 8 bytes after the beginning of the file.
128 * stderr: Used to print out error messages.
129 */
130 static uint32_t fletcher32(const void *data, int length)
131 {
132 uint32_t c0;
133 uint32_t c1;
134 uint32_t checksum;
135 int index;
136 const uint16_t *pptr = data;
137
138 length /= 2;
139
140 c0 = 0xFFFF;
141 c1 = 0xFFFF;
142
143 while (length) {
144 index = length >= 359 ? 359 : length;
145 length -= index;
146 do {
147 c0 += *(pptr++);
148 c1 += c0;
149 } while (--index);
150 c0 = (c0 & 0xFFFF) + (c0 >> 16);
151 c1 = (c1 & 0xFFFF) + (c1 >> 16);
152 }
153
154 /* Sums[0,1] mod 64K + overflow */
155 c0 = (c0 & 0xFFFF) + (c0 >> 16);
156 c1 = (c1 & 0xFFFF) + (c1 >> 16);
157 checksum = (c1 << 16) | c0;
158
159 return checksum;
160 }
161
162 amd_fw_entry amd_psp_fw_table[] = {
163 { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
164 { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB,
165 .generate_manifest = true },
166 { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB },
167 { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 },
168 { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
169 { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH },
170 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB,
171 .generate_manifest = true },
172 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
173 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
174 { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB,
175 .skip_hashing = true },
176 { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB },
177 { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB },
178 { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB },
179 { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB },
180 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB },
181 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
182 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
183 { .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
184 { .type = AMD_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
185 { .type = AMD_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
186 { .type = AMD_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
187 { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB },
188 { .type = AMD_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
189 { .type = AMD_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
190 { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
191 { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB },
192 { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
193 { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
194 { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
195 { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
196 { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
197 { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB },
198 { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB },
199 { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB },
200 { .type = AMD_FW_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB },
201 { .type = AMD_FW_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB },
202 { .type = AMD_FW_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB },
203 { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB },
204 { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB,
205 .generate_manifest = true },
206 { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB },
207 { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB },
208 { .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB },
209 { .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB },
210 { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB },
211 { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB },
212 { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB },
213 { .type = AMD_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB },
214 { .type = AMD_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB },
215 { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB },
216 { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB },
217 { .type = AMD_FW_DXIO, .level = PSP_BOTH | PSP_BOTH_AB },
218 { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB },
219 { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB },
220 { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB },
221 { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB },
222 { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB },
223 { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB },
224 { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB },
225 { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
226 { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB },
227 { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB },
228 { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB },
229 { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
230 { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB },
231 { .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB },
232 { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB },
233 { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB },
234 { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB,
235 .generate_manifest = true },
236 { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
237 { .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
238 { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB },
239 { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
240 { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB },
241 { .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB },
242 { .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
243 { .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
244 { .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
245 { .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB },
246 { .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
247 { .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
248 { .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB },
249 { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
250 { .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB },
251 { .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB },
252 { .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB },
253 { .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB },
254 { .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB },
255 { .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB },
256 { .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
257 { .type = AMD_FW_INVALID },
258 };
259
260 amd_fw_entry amd_fw_table[] = {
261 { .type = AMD_FW_XHCI },
262 { .type = AMD_FW_IMC },
263 { .type = AMD_FW_GEC },
264 { .type = AMD_FW_INVALID },
265 };
266
267 amd_bios_entry amd_bios_table[] = {
268 { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH },
269 { .type = AMD_BIOS_SIG, .inst = 0, .level = BDT_BOTH },
270 { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH },
271 { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH },
272 { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH },
273 { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH },
274 { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH },
275 { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH },
276 { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH },
277 { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH },
278 { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH },
279 { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH },
280 { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH },
281 { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH },
282 { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH },
283 { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH },
284 { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH },
285 { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH },
286 { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH },
287 { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH },
288 { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH },
289 { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH },
290 { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH },
291 { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH },
292 { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH },
293 { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH },
294 { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH },
295 { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH },
296 { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH },
297 { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH },
298 { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH },
299 { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH },
300 { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH },
301 { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH },
302 { .type = AMD_BIOS_APOB, .level = BDT_BOTH },
303 { .type = AMD_BIOS_BIN,
304 .reset = 1, .copy = 1, .zlib = 1, .inst = 0, .level = BDT_BOTH },
305 { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 },
306 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH },
307 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH },
308 { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH },
309 { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH },
310 { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 0, .level = BDT_BOTH },
311 { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 0, .level = BDT_BOTH },
312 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH },
313 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH },
314 { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 0, .level = BDT_BOTH },
315 { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 0, .level = BDT_BOTH },
316 { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 0, .level = BDT_BOTH },
317 { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 0, .level = BDT_BOTH },
318 { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 0, .level = BDT_BOTH },
319 { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 0, .level = BDT_BOTH },
320 { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 0, .level = BDT_BOTH },
321 { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 0, .level = BDT_BOTH },
322 { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 0, .level = BDT_BOTH },
323 { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 0, .level = BDT_BOTH },
324 { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 0, .level = BDT_BOTH },
325 { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 0, .level = BDT_BOTH },
326 { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 0, .level = BDT_BOTH },
327 { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 0, .level = BDT_BOTH },
328 { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 0, .level = BDT_BOTH },
329 { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 0, .level = BDT_BOTH },
330 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH },
331 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH },
332 { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH },
333 { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH },
334 { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 1, .level = BDT_BOTH },
335 { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 1, .level = BDT_BOTH },
336 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH },
337 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH },
338 { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 1, .level = BDT_BOTH },
339 { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 1, .level = BDT_BOTH },
340 { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 1, .level = BDT_BOTH },
341 { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 1, .level = BDT_BOTH },
342 { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 1, .level = BDT_BOTH },
343 { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 1, .level = BDT_BOTH },
344 { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 1, .level = BDT_BOTH },
345 { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 1, .level = BDT_BOTH },
346 { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 1, .level = BDT_BOTH },
347 { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 1, .level = BDT_BOTH },
348 { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 1, .level = BDT_BOTH },
349 { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 1, .level = BDT_BOTH },
350 { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 1, .level = BDT_BOTH },
351 { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 1, .level = BDT_BOTH },
352 { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 1, .level = BDT_BOTH },
353 { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 1, .level = BDT_BOTH },
354 { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 },
355 { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 },
356 { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 },
357 { .type = AMD_BIOS_UCODE, .inst = 3, .level = BDT_LVL2 },
358 { .type = AMD_BIOS_UCODE, .inst = 4, .level = BDT_LVL2 },
359 { .type = AMD_BIOS_UCODE, .inst = 5, .level = BDT_LVL2 },
360 { .type = AMD_BIOS_UCODE, .inst = 6, .level = BDT_LVL2 },
361 { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 },
362 { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH },
363 { .type = AMD_BIOS_INVALID },
364 };
365
366 #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
367 #define RUN_OFFSET_MODE(ctx, offset, mode) \
368 ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \
369 ((mode) == AMD_ADDR_REL_BIOS ? (offset) : \
370 ((mode) == AMD_ADDR_REL_TAB ? (offset) - (ctx).current_table : (offset))))
371 #define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode)
372 #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \
373 (run) - RUN_BASE(ctx) : (run)) /* TODO: */
374 #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
375 /* The mode in entry can not be higher than the header's.
376 For example, if table mode is 0, all the entry mode will be 0. */
377 #define RUN_CURRENT_MODE(ctx, mode) RUN_OFFSET_MODE((ctx), (ctx).current, \
378 (ctx).address_mode < (mode) ? (ctx).address_mode : (mode))
379 #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
380 #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
381 #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom))
382 #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \
383 (ctx).address_mode < (mode) ? (ctx).address_mode : (mode))
384 #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
385 /* Only set the address mode in entry if the table is mode 2. */
386 #define SET_ADDR_MODE(table, mode) \
387 ((table)->header.additional_info_fields.address_mode == \
388 AMD_ADDR_REL_TAB ? (mode) : 0)
389 #define SET_ADDR_MODE_BY_TABLE(table) \
390 SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode)
391
392
393 static void free_psp_firmware_filenames(amd_fw_entry *fw_table)
394 {
395 amd_fw_entry *index;
396
397 for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
398 if (index->filename &&
399 index->type != AMD_FW_VERSTAGE_SIG &&
400 index->type != AMD_FW_PSP_VERSTAGE &&
401 index->type != AMD_FW_SPL &&
402 index->type != AMD_FW_PSP_WHITELIST) {
403 free(index->filename);
404 index->filename = NULL;
405 }
406 }
407 }
408
409 static void free_bdt_firmware_filenames(amd_bios_entry *fw_table)
410 {
411 amd_bios_entry *index;
412
413 for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) {
414 if (index->filename &&
415 index->type != AMD_BIOS_APCB &&
416 index->type != AMD_BIOS_BIN &&
417 index->type != AMD_BIOS_APCB_BK &&
418 index->type != AMD_BIOS_UCODE) {
419 free(index->filename);
420 index->filename = NULL;
421 }
422 }
423 }
424
425 static void amdfwtool_cleanup(context *ctx)
426 {
427 free(ctx->rom);
428 ctx->rom = NULL;
429
430 /* Free the filename. */
431 free_psp_firmware_filenames(amd_psp_fw_table);
432 free_bdt_firmware_filenames(amd_bios_table);
433
434 free(ctx->amd_psp_fw_table_clean);
435 ctx->amd_psp_fw_table_clean = NULL;
436 free(ctx->amd_bios_table_clean);
437 ctx->amd_bios_table_clean = NULL;
438 }
439
440 void assert_fw_entry(uint32_t count, uint32_t max, context *ctx)
441 {
442 if (count >= max) {
443 fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items "
444 "(%d)\n", count, max);
445 amdfwtool_cleanup(ctx);
446 exit(1);
447 }
448 }
449
450 static void set_current_pointer(context *ctx, uint32_t value)
451 {
452 if (ctx->current_pointer_saved != 0xFFFFFFFF &&
453 ctx->current_pointer_saved != ctx->current) {
454 fprintf(stderr, "Error: The pointer is changed elsewhere\n");
455 amdfwtool_cleanup(ctx);
456 exit(1);
457 }
458
459 ctx->current = value;
460
461 if (ctx->current > ctx->rom_size) {
462 fprintf(stderr, "Error: Packing data causes overflow\n");
463 amdfwtool_cleanup(ctx);
464 exit(1);
465 }
466
467 ctx->current_pointer_saved = ctx->current;
468 }
469
470 static void adjust_current_pointer(context *ctx, uint32_t add, uint32_t align)
471 {
472 /* Get */
473 set_current_pointer(ctx, ALIGN_UP(ctx->current + add, align));
474 }
475
476 static void *new_psp_dir(context *ctx, int multi)
477 {
478 void *ptr;
479
480 /*
481 * Force both onto boundary when multi. Primary table is after
482 * updatable table, so alignment ensures primary can stay intact
483 * if secondary is reprogrammed.
484 */
485 if (multi)
486 adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT);
487 else
488 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
489
490 ptr = BUFF_CURRENT(*ctx);
491 ((psp_directory_header *)ptr)->num_entries = 0;
492 ((psp_directory_header *)ptr)->additional_info = 0;
493 ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode;
494 adjust_current_pointer(ctx,
495 sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry),
496 1);
497 return ptr;
498 }
499
500 static void *new_ish_dir(context *ctx)
501 {
502 void *ptr;
503 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
504 ptr = BUFF_CURRENT(*ctx);
505 adjust_current_pointer(ctx, TABLE_ALIGNMENT, 1);
506
507 return ptr;
508 }
509
510 static void *new_combo_dir(context *ctx)
511 {
512 void *ptr;
513
514 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
515 ptr = BUFF_CURRENT(*ctx);
516 adjust_current_pointer(ctx,
517 sizeof(psp_combo_header) + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry),
518 1);
519 return ptr;
520 }
521
522 static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx)
523 {
524 psp_combo_directory *cdir = directory;
525 psp_directory_table *dir = directory;
526 bios_directory_table *bdir = directory;
527 uint32_t table_size = 0;
528
529 if (ctx == NULL || directory == NULL) {
530 fprintf(stderr, "Calling %s with NULL pointers\n", __func__);
531 return;
532 }
533
534 /* The table size needs to be 0x1000 aligned. So align the end of table. */
535 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
536
537 switch (cookie) {
538 case PSP2_COOKIE:
539 case BHD2_COOKIE:
540 cdir->header.cookie = cookie;
541 /* lookup mode is hardcoded for now. */
542 cdir->header.lookup = 1;
543 cdir->header.num_entries = count;
544 cdir->header.reserved[0] = 0;
545 cdir->header.reserved[1] = 0;
546 /* checksum everything that comes after the Checksum field */
547 cdir->header.checksum = fletcher32(&cdir->header.num_entries,
548 count * sizeof(psp_combo_entry)
549 + sizeof(cdir->header.num_entries)
550 + sizeof(cdir->header.lookup)
551 + 2 * sizeof(cdir->header.reserved[0]));
552 break;
553 case PSP_COOKIE:
554 case PSPL2_COOKIE:
555 /* The table size is only set once. Later calls only update
556 * the count and fletcher. So does the BIOS table. */
557 if (dir->header.additional_info_fields.dir_size == 0) {
558 table_size = ctx->current - ctx->current_table;
559 if ((table_size % TABLE_ALIGNMENT) != 0 &&
560 (table_size / TABLE_ALIGNMENT) != 0) {
561 fprintf(stderr, "The PSP table size should be 4K aligned\n");
562 amdfwtool_cleanup(ctx);
563 exit(1);
564 }
565 dir->header.additional_info_fields.dir_size =
566 table_size / TABLE_ALIGNMENT;
567 }
568 dir->header.cookie = cookie;
569 dir->header.num_entries = count;
570 dir->header.additional_info_fields.spi_block_size = 1;
571 dir->header.additional_info_fields.base_addr = 0;
572 /* checksum everything that comes after the Checksum field */
573 dir->header.checksum = fletcher32(&dir->header.num_entries,
574 count * sizeof(psp_directory_entry)
575 + sizeof(dir->header.num_entries)
576 + sizeof(dir->header.additional_info));
577 break;
578 case BHD_COOKIE:
579 case BHDL2_COOKIE:
580 if (bdir->header.additional_info_fields.dir_size == 0) {
581 table_size = ctx->current - ctx->current_table;
582 if ((table_size % TABLE_ALIGNMENT) != 0 &&
583 table_size / TABLE_ALIGNMENT != 0) {
584 fprintf(stderr, "The BIOS table size should be 4K aligned\n");
585 amdfwtool_cleanup(ctx);
586 exit(1);
587 }
588 bdir->header.additional_info_fields.dir_size =
589 table_size / TABLE_ALIGNMENT;
590 }
591 bdir->header.cookie = cookie;
592 bdir->header.num_entries = count;
593 bdir->header.additional_info_fields.spi_block_size = 1;
594 bdir->header.additional_info_fields.base_addr = 0;
595 /* checksum everything that comes after the Checksum field */
596 bdir->header.checksum = fletcher32(&bdir->header.num_entries,
597 count * sizeof(bios_directory_entry)
598 + sizeof(bdir->header.num_entries)
599 + sizeof(bdir->header.additional_info));
600 break;
601 }
602
603 }
604
605 static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdir,
606 context *ctx, amd_cb_config *cb_config)
607 {
608 switch (cb_config->soc_id) {
609 case PLATFORM_UNKNOWN:
610 amd_romsig->psp_directory =
611 BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS);
612 break;
613 case PLATFORM_CEZANNE:
614 case PLATFORM_MENDOCINO:
615 case PLATFORM_PHOENIX:
616 case PLATFORM_GLINDA:
617 case PLATFORM_CARRIZO:
618 case PLATFORM_STONEYRIDGE:
619 case PLATFORM_RAVEN:
620 case PLATFORM_PICASSO:
621 case PLATFORM_LUCIENNE:
622 case PLATFORM_RENOIR:
623 case PLATFORM_GENOA:
624 default:
625 /* for combo, it is also combo_psp_directory */
626 amd_romsig->new_psp_directory =
627 BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS);
628 break;
629 }
630 }
631
632 static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *biosdir,
633 context *ctx, amd_cb_config *cb_config)
634 {
635 switch (cb_config->soc_id) {
636 case PLATFORM_RENOIR:
637 case PLATFORM_LUCIENNE:
638 case PLATFORM_CEZANNE:
639 case PLATFORM_GENOA:
640 if (!cb_config->recovery_ab)
641 amd_romsig->bios3_entry =
642 BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS);
643 break;
644 case PLATFORM_MENDOCINO:
645 case PLATFORM_PHOENIX:
646 case PLATFORM_GLINDA:
647 break;
648 case PLATFORM_CARRIZO:
649 case PLATFORM_STONEYRIDGE:
650 case PLATFORM_RAVEN:
651 case PLATFORM_PICASSO:
652 default:
653 amd_romsig->bios1_entry =
654 BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS);
655 break;
656 }
657 }
658
659 static uint32_t get_psp_id(enum platform soc_id)
660 {
661 uint32_t psp_id;
662 switch (soc_id) {
663 case PLATFORM_RAVEN:
664 case PLATFORM_PICASSO:
665 psp_id = 0xBC0A0000;
666 break;
667 case PLATFORM_RENOIR:
668 case PLATFORM_LUCIENNE:
669 psp_id = 0xBC0C0000;
670 break;
671 case PLATFORM_CEZANNE:
672 psp_id = 0xBC0C0140;
673 break;
674 case PLATFORM_MENDOCINO:
675 psp_id = 0xBC0D0900;
676 break;
677 case PLATFORM_STONEYRIDGE:
678 psp_id = 0x10220B00;
679 break;
680 case PLATFORM_GLINDA:
681 psp_id = 0xBC0E0200;
682 break;
683 case PLATFORM_PHOENIX:
684 psp_id = 0xBC0D0400;
685 break;
686 case PLATFORM_GENOA:
687 psp_id = 0xBC0C0111;
688 break;
689 case PLATFORM_CARRIZO:
690 default:
691 psp_id = 0;
692 break;
693 }
694 return psp_id;
695 }
696
697 static void integrate_firmwares(context *ctx,
698 embedded_firmware *romsig,
699 amd_fw_entry *fw_table)
700 {
701 ssize_t bytes;
702 uint32_t i;
703
704 adjust_current_pointer(ctx, 0, BLOB_ALIGNMENT);
705
706 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
707 if (fw_table[i].filename != NULL) {
708 switch (fw_table[i].type) {
709 case AMD_FW_IMC:
710 adjust_current_pointer(ctx, 0, 0x10000U);
711 romsig->imc_entry = RUN_CURRENT(*ctx);
712 break;
713 case AMD_FW_GEC:
714 romsig->gec_entry = RUN_CURRENT(*ctx);
715 break;
716 case AMD_FW_XHCI:
717 romsig->xhci_entry = RUN_CURRENT(*ctx);
718 break;
719 default:
720 /* Error */
721 break;
722 }
723
724 bytes = copy_blob(BUFF_CURRENT(*ctx),
725 fw_table[i].filename, BUFF_ROOM(*ctx));
726 if (bytes < 0) {
727 amdfwtool_cleanup(ctx);
728 exit(1);
729 }
730
731 adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT);
732 }
733 }
734 }
735
736 static void output_manifest(int manifest_fd, amd_fw_entry *fw_entry)
737 {
738 struct amd_fw_header hdr;
739 int blob_fd;
740 ssize_t bytes;
741
742 blob_fd = open(fw_entry->filename, O_RDONLY);
743 if (blob_fd < 0) {
744 fprintf(stderr, "Error opening file: %s: %s\n",
745 fw_entry->filename, strerror(errno));
746 return;
747 }
748
749 bytes = read(blob_fd, &hdr, sizeof(hdr));
750 if (bytes != sizeof(hdr)) {
751 close(blob_fd);
752 fprintf(stderr, "Error while reading %s\n", fw_entry->filename);
753 return;
754 }
755
756 dprintf(manifest_fd, "type: 0x%02x ver:%02x.%02x.%02x.%02x\n",
757 fw_entry->type, hdr.version[3], hdr.version[2],
758 hdr.version[1], hdr.version[0]);
759
760 close(blob_fd);
761
762 }
763
764 static void dump_blob_version(char *manifest_file, amd_fw_entry *fw_table)
765 {
766 amd_fw_entry *index;
767 int manifest_fd;
768
769 manifest_fd = open(manifest_file, O_WRONLY | O_CREAT | O_TRUNC, 0666);
770 if (manifest_fd < 0) {
771 fprintf(stderr, "Error opening file: %s: %s\n",
772 manifest_file, strerror(errno));
773 return;
774 }
775
776 for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
777 if (!(index->filename))
778 continue;
779
780 if (index->generate_manifest == true)
781 output_manifest(manifest_fd, index);
782 }
783
784 close(manifest_fd);
785 }
786
787 /* For debugging */
788 static void dump_psp_firmwares(amd_fw_entry *fw_table)
789 {
790 amd_fw_entry *index;
791
792 printf("PSP firmware components:\n");
793 for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
794 if (index->type == AMD_PSP_FUSE_CHAIN)
795 printf(" %2x: level=%x, subprog=%x, inst=%x\n",
796 index->type, index->level, index->subprog, index->inst);
797 else if (index->filename)
798 printf(" %2x: level=%x, subprog=%x, inst=%x, %s\n",
799 index->type, index->level, index->subprog, index->inst,
800 index->filename);
801 }
802 }
803
804 static void dump_bdt_firmwares(amd_bios_entry *fw_table)
805 {
806 amd_bios_entry *index;
807
808 printf("BIOS Directory Table (BDT) components:\n");
809 for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) {
810 if (index->filename)
811 printf(" %2x: level=%x, %s\n",
812 index->type, index->level, index->filename);
813 }
814 }
815
816 static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir,
817 psp_directory_table *pspdir2, ish_directory_table *ish,
818 amd_fw_type ab, enum platform soc_id)
819 {
820 uint32_t count;
821 uint32_t current_table_save;
822
823 current_table_save = ctx->current_table;
824 ctx->current_table = (char *)pspdir - ctx->rom;
825 count = pspdir->header.num_entries;
826 assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
827 pspdir->entries[count].type = (uint8_t)ab;
828 pspdir->entries[count].subprog = 0;
829 pspdir->entries[count].rsvd = 0;
830 if (ish != NULL) {
831 ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
832 ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1;
833 ish->update_retry_count = 2;
834 ish->glitch_retry_count = 0;
835 ish->psp_id = get_psp_id(soc_id);
836 ish->checksum = fletcher32(&ish->boot_priority,
837 sizeof(ish_directory_table) - sizeof(uint32_t));
838 pspdir->entries[count].addr =
839 BUFF_TO_RUN_MODE(*ctx, ish, AMD_ADDR_REL_BIOS);
840 pspdir->entries[count].address_mode =
841 SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
842 pspdir->entries[count].size = TABLE_ALIGNMENT;
843 } else {
844 pspdir->entries[count].addr =
845 BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
846 pspdir->entries[count].address_mode =
847 SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
848 pspdir->entries[count].size = _MAX(TABLE_ALIGNMENT,
849 pspdir2->header.num_entries *
850 sizeof(psp_directory_entry) +
851 sizeof(psp_directory_header));
852 }
853
854 count++;
855 pspdir->header.num_entries = count;
856 ctx->current_table = current_table_save;
857 }
858
859 static void integrate_psp_firmwares(context *ctx,
860 psp_directory_table *pspdir,
861 psp_directory_table *pspdir2,
862 psp_directory_table *pspdir2_b,
863 amd_fw_entry *fw_table,
864 uint32_t cookie,
865 amd_cb_config *cb_config)
866 {
867 ssize_t bytes;
868 unsigned int i, count;
869 int level;
870 uint32_t size;
871 uint64_t addr;
872 uint32_t current_table_save;
873 bool recovery_ab = cb_config->recovery_ab;
874 ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL;
875 bool use_only_a = (cb_config->soc_id == PLATFORM_PHOENIX); /* TODO: b:285390041 */
876
877 /* This function can create a primary table, a secondary table, or a
878 * flattened table which contains all applicable types. These if-else
879 * statements infer what the caller intended. If a 2nd-level cookie
880 * is passed, clearly a 2nd-level table is intended. However, a
881 * 1st-level cookie may indicate level 1 or flattened.
882 */
883 if (!cb_config->multi_level)
884 level = PSP_BOTH;
885 else if (cookie == PSPL2_COOKIE)
886 level = PSP_LVL2;
887 else if (cookie == PSP_COOKIE)
888 level = PSP_LVL1;
889 else
890 level = PSP_BOTH;
891
892 if (recovery_ab) {
893 if (cookie == PSPL2_COOKIE)
894 level = PSP_LVL2_AB;
895 else if (cookie == PSP_COOKIE)
896 level = PSP_LVL1_AB;
897 else
898 level = PSP_BOTH_AB;
899 }
900 current_table_save = ctx->current_table;
901 ctx->current_table = (char *)pspdir - ctx->rom;
902 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
903
904 for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
905 if (!(fw_table[i].level & level))
906 continue;
907
908 assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
909
910 if (fw_table[i].type == AMD_TOKEN_UNLOCK) {
911 if (!fw_table[i].other)
912 continue;
913 adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
914 pspdir->entries[count].type = fw_table[i].type;
915 pspdir->entries[count].size = 4096; /* TODO: doc? */
916 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
917 pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir);
918 pspdir->entries[count].subprog = fw_table[i].subprog;
919 pspdir->entries[count].rsvd = 0;
920 adjust_current_pointer(ctx, 4096, 0x100U);
921 count++;
922 } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
923 pspdir->entries[count].type = fw_table[i].type;
924 pspdir->entries[count].subprog = fw_table[i].subprog;
925 pspdir->entries[count].rsvd = 0;
926 pspdir->entries[count].size = 0xFFFFFFFF;
927 pspdir->entries[count].addr = fw_table[i].other;
928 pspdir->entries[count].address_mode = 0;
929 count++;
930 } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
931 if (fw_table[i].filename == NULL) {
932 if (fw_table[i].size == 0)
933 continue;
934 size = fw_table[i].size;
935 addr = fw_table[i].dest;
936 if (addr != ALIGN_UP(addr, ERASE_ALIGNMENT)) {
937 fprintf(stderr,
938 "Error: PSP NVRAM section not aligned with erase block size.\n\n");
939 amdfwtool_cleanup(ctx);
940 exit(1);
941 }
942 } else {
943 adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
944 bytes = copy_blob(BUFF_CURRENT(*ctx),
945 fw_table[i].filename, BUFF_ROOM(*ctx));
946 if (bytes <= 0) {
947 amdfwtool_cleanup(ctx);
948 exit(1);
949 }
950
951 size = ALIGN_UP(bytes, ERASE_ALIGNMENT);
952 addr = RUN_CURRENT(*ctx);
953 adjust_current_pointer(ctx, bytes, BLOB_ERASE_ALIGNMENT);
954 }
955
956 pspdir->entries[count].type = fw_table[i].type;
957 pspdir->entries[count].subprog = fw_table[i].subprog;
958 pspdir->entries[count].rsvd = 0;
959 pspdir->entries[count].size = size;
960 pspdir->entries[count].addr = addr;
961
962 pspdir->entries[count].address_mode =
963 SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
964
965 count++;
966 } else if (fw_table[i].filename != NULL) {
967 if (fw_table[i].addr_signed) {
968 pspdir->entries[count].addr =
969 RUN_OFFSET(*ctx, fw_table[i].addr_signed);
970 pspdir->entries[count].address_mode =
971 SET_ADDR_MODE_BY_TABLE(pspdir);
972 bytes = fw_table[i].file_size;
973 } else {
974 bytes = copy_blob(BUFF_CURRENT(*ctx),
975 fw_table[i].filename, BUFF_ROOM(*ctx));
976 if (bytes < 0) {
977 amdfwtool_cleanup(ctx);
978 exit(1);
979 }
980 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
981 pspdir->entries[count].address_mode =
982 SET_ADDR_MODE_BY_TABLE(pspdir);
983 adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT);
984 }
985
986 pspdir->entries[count].type = fw_table[i].type;
987 pspdir->entries[count].subprog = fw_table[i].subprog;
988 pspdir->entries[count].rsvd = 0;
989 pspdir->entries[count].inst = fw_table[i].inst;
990 pspdir->entries[count].size = (uint32_t)bytes;
991
992 count++;
993 } else {
994 /* This APU doesn't have this firmware. */
995 }
996 }
997
998 fill_dir_header(pspdir, count, cookie, ctx);
999
1000 if (recovery_ab && (pspdir2 != NULL)) {
1001 if (cb_config->need_ish) { /* Need ISH */
1002 ish_a_dir = new_ish_dir(ctx);
1003 if (pspdir2_b != NULL)
1004 ish_b_dir = new_ish_dir(ctx);
1005 }
1006 pspdir->header.num_entries = count;
1007 integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir,
1008 AMD_FW_RECOVERYAB_A, cb_config->soc_id);
1009 if (pspdir2_b != NULL)
1010 integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir,
1011 use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B,
1012 cb_config->soc_id);
1013 else
1014 integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir,
1015 use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B,
1016 cb_config->soc_id);
1017
1018 count = pspdir->header.num_entries;
1019 } else if (pspdir2 != NULL) {
1020 assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
1021 pspdir->entries[count].type = AMD_FW_L2_PTR;
1022 pspdir->entries[count].subprog = 0;
1023 pspdir->entries[count].rsvd = 0;
1024 pspdir->entries[count].size = sizeof(pspdir2->header)
1025 + pspdir2->header.num_entries
1026 * sizeof(psp_directory_entry);
1027
1028 pspdir->entries[count].addr =
1029 BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
1030 pspdir->entries[count].address_mode =
1031 SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
1032 count++;
1033 }
1034
1035 fill_dir_header(pspdir, count, cookie, ctx);
1036 ctx->current_table = current_table_save;
1037 }
1038
1039 static void add_psp_firmware_entry(context *ctx,
1040 psp_directory_table *pspdir,
1041 void *table, amd_fw_type type, uint32_t size)
1042 {
1043 uint32_t count = pspdir->header.num_entries;
1044 uint32_t index;
1045 uint32_t current_table_save;
1046
1047 current_table_save = ctx->current_table;
1048 ctx->current_table = (char *)pspdir - ctx->rom;
1049
1050 /* If there is an entry of "type", replace it. */
1051 for (index = 0; index < count; index++) {
1052 if (pspdir->entries[index].type == (uint8_t)type)
1053 break;
1054 }
1055
1056 assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
1057 pspdir->entries[index].type = (uint8_t)type;
1058 pspdir->entries[index].subprog = 0;
1059 pspdir->entries[index].rsvd = 0;
1060 pspdir->entries[index].addr = BUFF_TO_RUN(*ctx, table);
1061 pspdir->entries[index].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir);
1062 pspdir->entries[index].size = size;
1063 if (index == count)
1064 count++;
1065
1066 fill_dir_header(pspdir, count, pspdir->header.cookie, ctx);
1067 ctx->current_table = current_table_save;
1068 }
1069
1070 static void *new_bios_dir(context *ctx, bool multi)
1071 {
1072 void *ptr;
1073
1074 /*
1075 * Force both onto boundary when multi. Primary table is after
1076 * updatable table, so alignment ensures primary can stay intact
1077 * if secondary is reprogrammed.
1078 */
1079 if (multi)
1080 adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT);
1081 else
1082 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
1083 ptr = BUFF_CURRENT(*ctx);
1084 ((bios_directory_hdr *) ptr)->additional_info = 0;
1085 ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode;
1086 adjust_current_pointer(ctx,
1087 sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry),
1088 1);
1089 return ptr;
1090 }
1091
1092 static int locate_bdt2_bios(bios_directory_table *level2,
1093 uint64_t *source, uint32_t *size)
1094 {
1095 uint32_t i;
1096
1097 *source = 0;
1098 *size = 0;
1099 if (!level2)
1100 return 0;
1101
1102 for (i = 0 ; i < level2->header.num_entries ; i++) {
1103 if (level2->entries[i].type == AMD_BIOS_BIN) {
1104 *source = level2->entries[i].source;
1105 *size = level2->entries[i].size;
1106 return 1;
1107 }
1108 }
1109 return 0;
1110 }
1111
1112 static int have_bios_tables(amd_bios_entry *table)
1113 {
1114 int i;
1115
1116 for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) {
1117 if (table[i].level & BDT_LVL1 && table[i].filename)
1118 return 1;
1119 }
1120 return 0;
1121 }
1122
1123 int find_bios_entry(amd_bios_type type)
1124 {
1125 int i;
1126
1127 for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) {
1128 if (amd_bios_table[i].type == type)
1129 return i;
1130 }
1131 return -1;
1132 }
1133
1134 static void add_bios_apcb_bk_entry(bios_directory_table *biosdir, unsigned int idx,
1135 int inst, uint32_t size, uint64_t source)
1136 {
1137 int i;
1138
1139 for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) {
1140 if (amd_bios_table[i].type == AMD_BIOS_APCB_BK &&
1141 amd_bios_table[i].inst == inst)
1142 break;
1143 }
1144
1145 if (amd_bios_table[i].type != AMD_BIOS_APCB_BK)
1146 return;
1147
1148 biosdir->entries[idx].type = amd_bios_table[i].type;
1149 biosdir->entries[idx].region_type = amd_bios_table[i].region_type;
1150 biosdir->entries[idx].dest = amd_bios_table[i].dest ?
1151 amd_bios_table[i].dest : (uint64_t)-1;
1152 biosdir->entries[idx].reset = amd_bios_table[i].reset;
1153 biosdir->entries[idx].copy = amd_bios_table[i].copy;
1154 biosdir->entries[idx].ro = amd_bios_table[i].ro;
1155 biosdir->entries[idx].compressed = amd_bios_table[i].zlib;
1156 biosdir->entries[idx].inst = amd_bios_table[i].inst;
1157 biosdir->entries[idx].subprog = amd_bios_table[i].subpr;
1158 biosdir->entries[idx].size = size;
1159 biosdir->entries[idx].source = source;
1160 biosdir->entries[idx].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
1161 }
1162
1163 static void integrate_bios_firmwares(context *ctx,
1164 bios_directory_table *biosdir,
1165 bios_directory_table *biosdir2,
1166 amd_bios_entry *fw_table,
1167 uint32_t cookie,
1168 amd_cb_config *cb_config)
1169 {
1170 ssize_t bytes;
1171 unsigned int i, count;
1172 int level;
1173 int apob_idx;
1174 uint32_t size;
1175 uint64_t source;
1176 uint32_t current_table_save;
1177
1178 /* This function can create a primary table, a secondary table, or a
1179 * flattened table which contains all applicable types. These if-else
1180 * statements infer what the caller intended. If a 2nd-level cookie
1181 * is passed, clearly a 2nd-level table is intended. However, a
1182 * 1st-level cookie may indicate level 1 or flattened.
1183 */
1184 if (!cb_config->multi_level)
1185 level = BDT_BOTH;
1186 else if (cookie == BHDL2_COOKIE)
1187 level = BDT_LVL2;
1188 else if (cookie == BHD_COOKIE)
1189 level = BDT_LVL1;
1190 else
1191 level = BDT_BOTH;
1192
1193 current_table_save = ctx->current_table;
1194 ctx->current_table = (char *)biosdir - ctx->rom;
1195 adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
1196
1197 for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) {
1198 if (!(fw_table[i].level & level))
1199 continue;
1200 if (fw_table[i].filename == NULL && (
1201 fw_table[i].type != AMD_BIOS_SIG &&
1202 fw_table[i].type != AMD_BIOS_APOB &&
1203 fw_table[i].type != AMD_BIOS_APOB_NV &&
1204 fw_table[i].type != AMD_BIOS_L2_PTR &&
1205 fw_table[i].type != AMD_BIOS_BIN &&
1206 fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM))
1207 continue;
1208
1209 /* BIOS Directory items may have additional requirements */
1210
1211 /* SIG needs a size, else no choice but to skip */
1212 if (fw_table[i].type == AMD_BIOS_SIG && !fw_table[i].size)
1213 continue;
1214
1215 /* Check APOB_NV requirements */
1216 if (fw_table[i].type == AMD_BIOS_APOB_NV) {
1217 if (!fw_table[i].size && !fw_table[i].src)
1218 continue; /* APOB_NV not used */
1219 if (fw_table[i].src && !fw_table[i].size) {
1220 fprintf(stderr, "Error: APOB NV address provided, but no size\n");
1221 amdfwtool_cleanup(ctx);
1222 exit(1);
1223 }
1224 /* If the APOB isn't used, APOB_NV isn't used either */
1225 apob_idx = find_bios_entry(AMD_BIOS_APOB);
1226 if (apob_idx < 0 || !fw_table[apob_idx].dest)
1227 continue; /* APOV NV not supported */
1228 }
1229
1230 /* APOB_DATA needs destination */
1231 if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) {
1232 fprintf(stderr, "Error: APOB destination not provided\n");
1233 amdfwtool_cleanup(ctx);
1234 exit(1);
1235 }
1236
1237 /* BIOS binary must have destination and uncompressed size. If
1238 * no filename given, then user must provide a source address.
1239 */
1240 if (fw_table[i].type == AMD_BIOS_BIN) {
1241 if (!fw_table[i].dest || !fw_table[i].size) {
1242 fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n");
1243 amdfwtool_cleanup(ctx);
1244 exit(1);
1245 }
1246 if (!fw_table[i].filename && !fw_table[i].src) {
1247 fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n");
1248 amdfwtool_cleanup(ctx);
1249 exit(1);
1250 }
1251 }
1252
1253 /* PSP_SHARED_MEM needs a destination and size */
1254 if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM &&
1255 (!fw_table[i].dest || !fw_table[i].size))
1256 continue;
1257 assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx);
1258
1259 biosdir->entries[count].type = fw_table[i].type;
1260 biosdir->entries[count].region_type = fw_table[i].region_type;
1261 biosdir->entries[count].dest = fw_table[i].dest ?
1262 fw_table[i].dest : (uint64_t)-1;
1263 biosdir->entries[count].reset = fw_table[i].reset;
1264 biosdir->entries[count].copy = fw_table[i].copy;
1265 biosdir->entries[count].ro = fw_table[i].ro;
1266 biosdir->entries[count].compressed = fw_table[i].zlib;
1267 biosdir->entries[count].inst = fw_table[i].inst;
1268 biosdir->entries[count].subprog = fw_table[i].subpr;
1269
1270 switch (fw_table[i].type) {
1271 case AMD_BIOS_SIG:
1272 /* Reserve size bytes within amdfw.rom */
1273 biosdir->entries[count].size = fw_table[i].size;
1274 biosdir->entries[count].source = RUN_CURRENT(*ctx);
1275 biosdir->entries[count].address_mode =
1276 SET_ADDR_MODE_BY_TABLE(biosdir);
1277 memset(BUFF_CURRENT(*ctx), 0xff,
1278 biosdir->entries[count].size);
1279 adjust_current_pointer(ctx, biosdir->entries[count].size, 0x100U);
1280 break;
1281 case AMD_BIOS_APOB:
1282 biosdir->entries[count].size = fw_table[i].size;
1283 biosdir->entries[count].source = fw_table[i].src;
1284 biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
1285 break;
1286 case AMD_BIOS_APOB_NV:
1287 if (fw_table[i].src) {
1288 /* If source is given, use that and its size */
1289 biosdir->entries[count].source = fw_table[i].src;
1290 biosdir->entries[count].address_mode =
1291 SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
1292 biosdir->entries[count].size = fw_table[i].size;
1293 } else {
1294 /* Else reserve size bytes within amdfw.rom */
1295 adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
1296 biosdir->entries[count].source = RUN_CURRENT(*ctx);
1297 biosdir->entries[count].address_mode =
1298 SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
1299 biosdir->entries[count].size = ALIGN_UP(
1300 fw_table[i].size, ERASE_ALIGNMENT);
1301 memset(BUFF_CURRENT(*ctx), 0xff,
1302 biosdir->entries[count].size);
1303 adjust_current_pointer(ctx, biosdir->entries[count].size, 1);
1304 }
1305 break;
1306 case AMD_BIOS_BIN:
1307 /* Don't make a 2nd copy, point to the same one */
1308 if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) {
1309 biosdir->entries[count].source = source;
1310 biosdir->entries[count].address_mode =
1311 SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
1312 biosdir->entries[count].size = size;
1313 break;
1314 }
1315
1316 /* level 2, or level 1 and no copy found in level 2 */
1317 biosdir->entries[count].source = fw_table[i].src;
1318 biosdir->entries[count].address_mode =
1319 SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
1320 biosdir->entries[count].dest = fw_table[i].dest;
1321 biosdir->entries[count].size = fw_table[i].size;
1322
1323 if (!fw_table[i].filename)
1324 break;
1325
1326 bytes = copy_blob(BUFF_CURRENT(*ctx),
1327 fw_table[i].filename, BUFF_ROOM(*ctx));
1328 if (bytes <= 0) {
1329 amdfwtool_cleanup(ctx);
1330 exit(1);
1331 }
1332
1333 biosdir->entries[count].source =
1334 RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS);
1335 biosdir->entries[count].address_mode =
1336 SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
1337
1338 adjust_current_pointer(ctx, bytes, 0x100U);
1339 break;
1340 case AMD_BIOS_PSP_SHARED_MEM:
1341 biosdir->entries[count].dest = fw_table[i].dest;
1342 biosdir->entries[count].size = fw_table[i].size;
1343 break;
1344
1345 default: /* everything else is copied from input */
1346 if (fw_table[i].type == AMD_BIOS_APCB ||
1347 fw_table[i].type == AMD_BIOS_APCB_BK)
1348 adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
1349 bytes = copy_blob(BUFF_CURRENT(*ctx),
1350 fw_table[i].filename, BUFF_ROOM(*ctx));
1351 if (bytes <= 0) {
1352 amdfwtool_cleanup(ctx);
1353 exit(1);
1354 }
1355
1356 biosdir->entries[count].size = (uint32_t)bytes;
1357 biosdir->entries[count].source = RUN_CURRENT(*ctx);
1358 biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
1359
1360 adjust_current_pointer(ctx, bytes, 0x100U);
1361 if (fw_table[i].type == AMD_BIOS_APCB && !cb_config->have_apcb_bk) {
1362 size = biosdir->entries[count].size;
1363 source = biosdir->entries[count].source;
1364 count++;
1365 add_bios_apcb_bk_entry(biosdir, count, fw_table[i].inst, size, source);
1366 }
1367 break;
1368 }
1369
1370 count++;
1371 }
1372
1373 fill_dir_header(biosdir, count, cookie, ctx);
1374
1375 if (biosdir2) {
1376 assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx);
1377 biosdir->entries[count].type = AMD_BIOS_L2_PTR;
1378 biosdir->entries[count].region_type = 0;
1379 biosdir->entries[count].size =
1380 + MAX_BIOS_ENTRIES
1381 * sizeof(bios_directory_entry);
1382 biosdir->entries[count].source =
1383 BUFF_TO_RUN(*ctx, biosdir2);
1384 biosdir->entries[count].address_mode =
1385 SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
1386 biosdir->entries[count].subprog = 0;
1387 biosdir->entries[count].inst = 0;
1388 biosdir->entries[count].copy = 0;
1389 biosdir->entries[count].compressed = 0;
1390 biosdir->entries[count].dest = -1;
1391 biosdir->entries[count].reset = 0;
1392 biosdir->entries[count].ro = 0;
1393 count++;
1394 }
1395
1396 fill_dir_header(biosdir, count, cookie, ctx);
1397 ctx->current_table = current_table_save;
1398 }
1399
1400 static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
1401 embedded_firmware *amd_romsig)
1402 {
1403 if ((cb_config->efs_spi_readmode == 0xFF) || (cb_config->efs_spi_speed == 0xFF)) {
1404 fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n");
1405 return 1;
1406 }
1407
1408 /* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
1409 * Leave as 0xffffffff for first gen */
1410 if (cb_config->second_gen) {
1411 amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
1412 amd_romsig->efs_gen.reserved = 0;
1413 } else {
1414 amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
1415 amd_romsig->efs_gen.reserved = ~0;
1416 }
1417
1418 switch (soc_id) {
1419 case PLATFORM_CARRIZO:
1420 case PLATFORM_STONEYRIDGE:
1421 amd_romsig->spi_readmode_f15_mod_60_6f = cb_config->efs_spi_readmode;
1422 amd_romsig->fast_speed_new_f15_mod_60_6f = cb_config->efs_spi_speed;
1423 break;
1424 case PLATFORM_RAVEN:
1425 case PLATFORM_PICASSO:
1426 amd_romsig->spi_readmode_f17_mod_00_2f = cb_config->efs_spi_readmode;
1427 amd_romsig->spi_fastspeed_f17_mod_00_2f = cb_config->efs_spi_speed;
1428 switch (cb_config->efs_spi_micron_flag) {
1429 case 0:
1430 amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff;
1431 break;
1432 case 1:
1433 amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa;
1434 break;
1435 default:
1436 fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n");
1437 return 1;
1438 }
1439 break;
1440 case PLATFORM_RENOIR:
1441 case PLATFORM_LUCIENNE:
1442 case PLATFORM_CEZANNE:
1443 case PLATFORM_MENDOCINO:
1444 case PLATFORM_PHOENIX:
1445 case PLATFORM_GLINDA:
1446 case PLATFORM_GENOA:
1447 amd_romsig->spi_readmode_f17_mod_30_3f = cb_config->efs_spi_readmode;
1448 amd_romsig->spi_fastspeed_f17_mod_30_3f = cb_config->efs_spi_speed;
1449 switch (cb_config->efs_spi_micron_flag) {
1450 case 0:
1451 amd_romsig->micron_detect_f17_mod_30_3f = 0xff;
1452 break;
1453 case 1:
1454 amd_romsig->micron_detect_f17_mod_30_3f = 0xaa;
1455 break;
1456 case 2:
1457 amd_romsig->micron_detect_f17_mod_30_3f = 0x55;
1458 break;
1459 default:
1460 fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n");
1461 return 1;
1462 }
1463 break;
1464 case PLATFORM_UNKNOWN:
1465 default:
1466 fprintf(stderr, "Error: Invalid SOC name.\n\n");
1467 return 1;
1468 }
1469 return 0;
1470 }
1471
1472 void open_process_config(char *config, amd_cb_config *cb_config)
1473 {
1474 FILE *config_handle;
1475
1476 if (config) {
1477 config_handle = fopen(config, "r");
1478 if (config_handle == NULL) {
1479 fprintf(stderr, "Can not open file %s for reading: %s\n",
1480 config, strerror(errno));
1481 exit(1);
1482 }
1483 if (process_config(config_handle, cb_config) == 0) {
1484 fprintf(stderr, "Configuration file %s parsing error\n",
1485 config);
1486 fclose(config_handle);
1487 exit(1);
1488 }
1489 fclose(config_handle);
1490 }
1491
1492 /* For debug. */
1493 if (cb_config->debug) {
1494 dump_psp_firmwares(amd_psp_fw_table);
1495 dump_bdt_firmwares(amd_bios_table);
1496 }
1497 }
1498
1499 static bool is_initial_alignment_required(enum platform soc_id)
1500 {
1501 switch (soc_id) {
1502 case PLATFORM_MENDOCINO:
1503 case PLATFORM_PHOENIX:
1504 case PLATFORM_GLINDA:
1505 return false;
1506 default:
1507 return true;
1508 }
1509 }
1510
1511 int main(int argc, char **argv)
1512 {
1513 int retval = 0;
1514 embedded_firmware *amd_romsig;
1515 psp_directory_table *pspdir = NULL;
1516 psp_directory_table *pspdir2 = NULL;
1517 psp_directory_table *pspdir2_b = NULL;
1518 psp_combo_directory *psp_combo_dir = NULL, *bhd_combo_dir = NULL;
1519 int combo_index = 0;
1520 int targetfd;
1521 context ctx = { 0 };
1522 uint32_t romsig_offset;
1523 amd_cb_config cb_config = {
1524 .efs_spi_readmode = 0xff, .efs_spi_speed = 0xff, .efs_spi_micron_flag = 0xff
1525 };
1526
1527 ctx.current_pointer_saved = 0xFFFFFFFF;
1528
1529 retval = amdfwtool_getopt(argc, argv, &cb_config, &ctx);
1530
1531 if (retval) {
1532 return retval;
1533 }
1534
1535 if (cb_config.use_combo) {
1536 ctx.amd_psp_fw_table_clean = malloc(sizeof(amd_psp_fw_table));
1537 ctx.amd_bios_table_clean = malloc(sizeof(amd_bios_table));
1538 memcpy(ctx.amd_psp_fw_table_clean, amd_psp_fw_table, sizeof(amd_psp_fw_table));
1539 memcpy(ctx.amd_bios_table_clean, amd_bios_table, sizeof(amd_bios_table));
1540 }
1541
1542 open_process_config(cb_config.config, &cb_config);
1543
1544 ctx.rom = malloc(ctx.rom_size);
1545 if (!ctx.rom) {
1546 fprintf(stderr, "Error: Failed to allocate memory\n");
1547 return 1;
1548 }
1549 memset(ctx.rom, 0xFF, ctx.rom_size);
1550
1551 romsig_offset = cb_config.efs_location ? cb_config.efs_location : AMD_ROMSIG_OFFSET;
1552 set_current_pointer(&ctx, romsig_offset);
1553
1554 amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
1555 amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
1556 amd_romsig->imc_entry = 0;
1557 amd_romsig->gec_entry = 0;
1558 amd_romsig->xhci_entry = 0;
1559
1560 if (cb_config.soc_id != PLATFORM_UNKNOWN) {
1561 retval = set_efs_table(cb_config.soc_id, &cb_config, amd_romsig);
1562 if (retval) {
1563 fprintf(stderr, "ERROR: Failed to initialize EFS table!\n");
1564 return retval;
1565 }
1566 } else {
1567 fprintf(stderr, "WARNING: No SOC name specified.\n");
1568 }
1569
1570 if (cb_config.need_ish)
1571 ctx.address_mode = AMD_ADDR_REL_TAB;
1572 else if (cb_config.second_gen)
1573 ctx.address_mode = AMD_ADDR_REL_BIOS;
1574 else
1575 ctx.address_mode = AMD_ADDR_PHYSICAL;
1576
1577 if (cb_config.efs_location != cb_config.body_location)
1578 set_current_pointer(&ctx, cb_config.body_location);
1579 else
1580 set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware));
1581
1582 integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
1583
1584 if (is_initial_alignment_required(cb_config.soc_id)) {
1585 /* TODO: Check for older platforms. */
1586 adjust_current_pointer(&ctx, 0, 0x10000U);
1587 }
1588 ctx.current_table = 0;
1589
1590 /* If the tool is invoked with command-line options to keep the signed PSP
1591 binaries separate, process the signed binaries first. */
1592 if (cb_config.signed_output_file && cb_config.signed_start_addr)
1593 process_signed_psp_firmwares(cb_config.signed_output_file,
1594 amd_psp_fw_table,
1595 cb_config.signed_start_addr,
1596 cb_config.soc_id);
1597
1598 if (cb_config.use_combo) {
1599 psp_combo_dir = new_combo_dir(&ctx);
1600
1601 adjust_current_pointer(&ctx, 0, 0x1000U);
1602
1603 if (!cb_config.recovery_ab)
1604 bhd_combo_dir = new_combo_dir(&ctx);
1605 }
1606
1607 combo_index = 0;
1608 if (cb_config.config)
1609 cb_config.combo_config[0] = cb_config.config;
1610
1611 do {
1612 if (cb_config.use_combo && cb_config.debug)
1613 printf("Processing %dth combo entry\n", combo_index);
1614
1615 /* for non-combo image, combo_config[0] == config, and
1616 * it already is processed. Actually "combo_index >
1617 * 0" is enough. Put both of them here to make sure
1618 * and make it clear this will not affect non-combo
1619 * case.
1620 */
1621 if (cb_config.use_combo && combo_index > 0) {
1622 /* Restore the table as clean data. */
1623 memcpy(amd_psp_fw_table, ctx.amd_psp_fw_table_clean,
1624 sizeof(amd_psp_fw_table));
1625 memcpy(amd_bios_table, ctx.amd_bios_table_clean,
1626 sizeof(amd_bios_table));
1627 assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx);
1628 open_process_config(cb_config.combo_config[combo_index], &cb_config);
1629
1630 /* In most cases, the address modes are same. */
1631 if (cb_config.need_ish)
1632 ctx.address_mode = AMD_ADDR_REL_TAB;
1633 else if (cb_config.second_gen)
1634 ctx.address_mode = AMD_ADDR_REL_BIOS;
1635 else
1636 ctx.address_mode = AMD_ADDR_PHYSICAL;
1637
1638 register_apcb_combo(&cb_config, combo_index, &ctx);
1639 }
1640
1641 if (cb_config.multi_level) {
1642 /* Do 2nd PSP directory followed by 1st */
1643 pspdir2 = new_psp_dir(&ctx, cb_config.multi_level);
1644 integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL,
1645 amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
1646 if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) {
1647 /* Create a copy of PSP Directory 2 in the backup slot B.
1648 Related biosdir2_b copy will be created later. */
1649 pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level);
1650 integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL,
1651 amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
1652 } else {
1653 /*
1654 * Either the platform is using only
1655 * one slot or B is same as above
1656 * directories for A. Skip creating
1657 * pspdir2_b here to save flash space.
1658 * Related biosdir2_b will be skipped
1659 * automatically.
1660 */
1661 pspdir2_b = NULL; /* More explicitly */
1662 }
1663 pspdir = new_psp_dir(&ctx, cb_config.multi_level);
1664 integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b,
1665 amd_psp_fw_table, PSP_COOKIE, &cb_config);
1666 } else {
1667 /* flat: PSP 1 cookie and no pointer to 2nd table */
1668 pspdir = new_psp_dir(&ctx, cb_config.multi_level);
1669 integrate_psp_firmwares(&ctx, pspdir, NULL, NULL,
1670 amd_psp_fw_table, PSP_COOKIE, &cb_config);
1671 }
1672
1673 if (!cb_config.use_combo) {
1674 fill_psp_directory_to_efs(amd_romsig, pspdir, &ctx, &cb_config);
1675 } else {
1676 fill_psp_directory_to_efs(amd_romsig, psp_combo_dir, &ctx, &cb_config);
1677 /* 0 -Compare PSP ID, 1 -Compare chip family ID */
1678 assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx);
1679 psp_combo_dir->entries[combo_index].id_sel = 0;
1680 psp_combo_dir->entries[combo_index].id = get_psp_id(cb_config.soc_id);
1681 psp_combo_dir->entries[combo_index].lvl2_addr =
1682 BUFF_TO_RUN_MODE(ctx, pspdir, AMD_ADDR_REL_BIOS);
1683
1684 fill_dir_header(psp_combo_dir, combo_index + 1, PSP2_COOKIE, &ctx);
1685 }
1686
1687 if (have_bios_tables(amd_bios_table)) {
1688 bios_directory_table *biosdir = NULL;
1689 if (cb_config.multi_level) {
1690 /* Do 2nd level BIOS directory followed by 1st */
1691 bios_directory_table *biosdir2 = NULL;
1692 bios_directory_table *biosdir2_b = NULL;
1693
1694 biosdir2 = new_bios_dir(&ctx, cb_config.multi_level);
1695
1696 integrate_bios_firmwares(&ctx, biosdir2, NULL,
1697 amd_bios_table, BHDL2_COOKIE, &cb_config);
1698 if (cb_config.recovery_ab) {
1699 if (pspdir2_b != NULL) {
1700 biosdir2_b = new_bios_dir(&ctx,
1701 cb_config.multi_level);
1702 integrate_bios_firmwares(&ctx, biosdir2_b, NULL,
1703 amd_bios_table, BHDL2_COOKIE,
1704 &cb_config);
1705 }
1706 add_psp_firmware_entry(&ctx, pspdir2, biosdir2,
1707 AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT);
1708 if (pspdir2_b != NULL)
1709 add_psp_firmware_entry(&ctx, pspdir2_b,
1710 biosdir2_b, AMD_FW_BIOS_TABLE,
1711 TABLE_ALIGNMENT);
1712 } else {
1713 biosdir = new_bios_dir(&ctx, cb_config.multi_level);
1714 integrate_bios_firmwares(&ctx, biosdir, biosdir2,
1715 amd_bios_table, BHD_COOKIE, &cb_config);
1716 }
1717 } else {
1718 /* flat: BHD1 cookie and no pointer to 2nd table */
1719 biosdir = new_bios_dir(&ctx, cb_config.multi_level);
1720 integrate_bios_firmwares(&ctx, biosdir, NULL,
1721 amd_bios_table, BHD_COOKIE, &cb_config);
1722 }
1723 if (!cb_config.use_combo) {
1724 fill_bios_directory_to_efs(amd_romsig, biosdir,
1725 &ctx, &cb_config);
1726 } else if (bhd_combo_dir != NULL) {
1727 /* In recovery A/B mode, there isn't a BHD combo directory.
1728 * Instead, the BIOS tables level 2 are linked by PSP tables.
1729 */
1730 fill_bios_directory_to_efs(amd_romsig, bhd_combo_dir,
1731 &ctx, &cb_config);
1732 assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx);
1733 bhd_combo_dir->entries[combo_index].id_sel = 0;
1734 bhd_combo_dir->entries[combo_index].id =
1735 get_psp_id(cb_config.soc_id);
1736 bhd_combo_dir->entries[combo_index].lvl2_addr =
1737 BUFF_TO_RUN_MODE(ctx, biosdir, AMD_ADDR_REL_BIOS);
1738
1739 fill_dir_header(bhd_combo_dir, combo_index + 1,
1740 BHD2_COOKIE, &ctx);
1741 }
1742 }
1743 } while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES &&
1744 cb_config.combo_config[combo_index] != NULL);
1745
1746 targetfd = open(cb_config.output, O_RDWR | O_CREAT | O_TRUNC, 0666);
1747 if (targetfd >= 0) {
1748 uint32_t offset = cb_config.efs_location;
1749 uint32_t bytes = cb_config.efs_location == cb_config.body_location ?
1750 ctx.current - offset : sizeof(*amd_romsig);
1751 uint32_t ret_bytes;
1752
1753 ret_bytes = write_from_buf_to_file(targetfd, BUFF_OFFSET(ctx, offset), bytes);
1754 if (bytes != ret_bytes) {
1755 fprintf(stderr, "Error: Writing to file %s failed\n", cb_config.output);
1756 retval = 1;
1757 }
1758 close(targetfd);
1759 } else {
1760 fprintf(stderr, "Error: could not open file: %s\n", cb_config.output);
1761 retval = 1;
1762 }
1763
1764 if (cb_config.efs_location != cb_config.body_location) {
1765 ssize_t bytes;
1766
1767 bytes = write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_location),
1768 ctx.current - cb_config.body_location);
1769 if (bytes != ctx.current - cb_config.body_location) {
1770 fprintf(stderr, "Error: Writing body\n");
1771 retval = 1;
1772 }
1773 }
1774
1775 if (cb_config.manifest_file) {
1776 dump_blob_version(cb_config.manifest_file, amd_psp_fw_table);
1777 }
1778
1779 amdfwtool_cleanup(&ctx);
1780 return retval;
1781 }
coreboot repo mirror