src/soc/amd/stoneyridge/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <drivers/i2c/designware/dw_i2c.h>
   8 #include <soc/acpi.h>
   9 #include <soc/cpu.h>
  10 #include <soc/northbridge.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/southbridge.h>
  13 #include <amdblocks/psp.h>
  14 #include <amdblocks/agesawrapper.h>
  15 #include <amdblocks/agesawrapper_call.h>
  16 #include <amdblocks/i2c.h>
  17 #include <amdblocks/post_codes.h>
  18
  19 #include "chip.h"
  20
  21 const char *soc_acpi_name(const struct device *dev)
  22 {
  23         if (dev->path.type == DEVICE_PATH_DOMAIN)
  24                 return "PCI0";
  25
  26         if (dev->path.type == DEVICE_PATH_USB) {
  27                 switch (dev->path.usb.port_type) {
  28                 case 0:
  29                         /* Root Hub */
  30                         return "RHUB";
  31                 case 2:
  32                         /* USB2 ports */
  33                         switch (dev->path.usb.port_id) {
  34                         case 0: return "HS01";
  35                         case 1: return "HS02";
  36                         case 2: return "HS03";
  37                         case 3: return "HS04";
  38                         case 4: return "HS05";
  39                         case 5: return "HS06";
  40                         case 6: return "HS07";
  41                         case 7: return "HS08";
  42                         }
  43                         break;
  44                 case 3:
  45                         /* USB3 ports */
  46                         switch (dev->path.usb.port_id) {
  47                         case 0: return "SS01";
  48                         case 1: return "SS02";
  49                         case 2: return "SS03";
  50                         }
  51                         break;
  52                 }
  53                 return NULL;
  54         }
  55
  56         if (dev->path.type != DEVICE_PATH_PCI)
  57                 return NULL;
  58
  59         switch (dev->path.pci.devfn) {
  60         case GFX_DEVFN:
  61                 return "IGFX";
  62         case PCIE0_DEVFN:
  63                 return "PBR4";
  64         case PCIE1_DEVFN:
  65                 return "PBR5";
  66         case PCIE2_DEVFN:
  67                 return "PBR6";
  68         case PCIE3_DEVFN:
  69                 return "PBR7";
  70         case PCIE4_DEVFN:
  71                 return "PBR8";
  72         case EHCI1_DEVFN:
  73                 return "EHC0";
  74         case SD_DEVFN:
  75                 return "SDCN";
  76         case XHCI_DEVFN:
  77                 return "XHC0";
  78         default:
  79                 return NULL;
  80         }
  81 };
  82
  83 struct device_operations stoneyridge_pci_domain_ops = {
  84         .read_resources   = domain_read_resources,
  85         .set_resources    = pci_domain_set_resources,
  86         .enable_resources = domain_enable_resources,
  87         .scan_bus         = pci_host_bridge_scan_bus,
  88         .acpi_name        = soc_acpi_name,
  89 };
  90
  91 static void soc_init(void *chip_info)
  92 {
  93         fch_init(chip_info);
  94 }
  95
  96 static void soc_final(void *chip_info)
  97 {
  98         fch_final(chip_info);
  99         fam15_finalize(chip_info);
 100 }
 101
 102 struct chip_operations soc_amd_stoneyridge_ops = {
 103         .name = "AMD StoneyRidge SOC",
 104         .init = soc_init,
 105         .final = soc_final
 106 };
 107
 108 static void earliest_ramstage(void *unused)
 109 {
 110         if (!acpi_is_wakeup_s3()) {
 111                 post_code(POSTCODE_PSP_LOAD_SMU);
 112                 if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 113                         psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
 114
 115                 post_code(POSTCODE_AGESA_AMDINITENV);
 116                 do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
 117         } else {
 118                 /* Complete the initial system restoration */
 119                 post_code(POSTCODE_AGESA_AMDS3LATERESTORE);
 120                 do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore");
 121         }
 122 }
 123
 124 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);