src/soc/amd/stoneyridge/northbridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <amdblocks/acpi.h>
   5 #include <amdblocks/biosram.h>
   6 #include <device/pci_ops.h>
   7 #include <arch/hpet.h>
   8 #include <arch/ioapic.h>
   9 #include <arch/vga.h>
  10 #include <acpi/acpi.h>
  11 #include <acpi/acpigen.h>
  12 #include <cbmem.h>
  13 #include <console/console.h>
  14 #include <cpu/amd/mtrr.h>
  15 #include <cpu/x86/lapic_def.h>
  16 #include <cpu/x86/msr.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20 #include <amdblocks/agesawrapper.h>
  21 #include <amdblocks/agesawrapper_call.h>
  22 #include <amdblocks/ioapic.h>
  23 #include <agesa_headers.h>
  24 #include <soc/cpu.h>
  25 #include <soc/northbridge.h>
  26 #include <soc/pci_devs.h>
  27 #include <soc/iomap.h>
  28 #include <static.h>
  29 #include <stdint.h>
  30 #include <string.h>
  31
  32 #include "chip.h"
  33
  34 static void read_resources(struct device *dev)
  35 {
  36         unsigned int idx = 0;
  37
  38         /* The northbridge has no PCI BARs implemented, so there's no need to call
  39            pci_dev_read_resources for it */
  40
  41         /*
  42          * This MMCONF resource must be reserved in the PCI domain.
  43          * It is not honored by the coreboot resource allocator if it is in
  44          * the CPU_CLUSTER.
  45          */
  46         mmconf_resource(dev, idx++);
  47 }
  48
  49 /**
  50  * I tried to reuse the resource allocation code in set_resource()
  51  * but it is too difficult to deal with the resource allocation magic.
  52  */
  53
  54 static void create_vga_resource(struct device *dev)
  55 {
  56         if (!dev->downstream)
  57                 return;
  58         if (!(dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA))
  59                 return;
  60
  61         printk(BIOS_DEBUG, "VGA: %s has VGA device\n",  dev_path(dev));
  62         /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
  63         pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
  64 }
  65
  66 static void set_resources(struct device *dev)
  67 {
  68         /* do we need this? */
  69         create_vga_resource(dev);
  70
  71         if (dev->downstream && dev->downstream->children)
  72                 assign_resources(dev->downstream);
  73 }
  74
  75 static void northbridge_init(struct device *dev)
  76 {
  77         register_new_ioapic(IO_APIC2_ADDR);
  78 }
  79
  80 /* Used by \_SB.PCI0._CRS */
  81 static void acpi_fill_root_complex_tom(const struct device *device)
  82 {
  83         const char *scope;
  84
  85         assert(device);
  86
  87         scope = acpi_device_scope(device);
  88         assert(scope);
  89         acpigen_write_scope(scope);
  90
  91         acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb());
  92
  93         /*
  94          * Since XP only implements parts of ACPI 2.0, we can't use a qword
  95          * here.
  96          * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
  97          * slide 22ff.
  98          * Shift value right by 20 bit to make it fit into 32bit,
  99          * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
 100          */
 101         acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20);
 102         acpigen_pop_len();
 103 }
 104
 105 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 106 {
 107         void *addr, *current;
 108
 109         /* Skip the HEST header. */
 110         current = (void *)(hest + 1);
 111
 112         addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
 113         if (addr != NULL)
 114                 current += acpi_create_hest_error_source(hest, current, 0,
 115                                 (void *)((u32)addr + 2), *(uint16_t *)addr - 2);
 116
 117         addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
 118         if (addr != NULL)
 119                 current += acpi_create_hest_error_source(hest, current, 1,
 120                                 (void *)((u32)addr + 2), *(uint16_t *)addr - 2);
 121
 122         return (unsigned long)current;
 123 }
 124
 125 unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
 126                                     acpi_rsdp_t *rsdp)
 127 {
 128         acpi_srat_t *srat;
 129         acpi_slit_t *slit;
 130         acpi_header_t *alib;
 131         acpi_header_t *ivrs;
 132         acpi_hest_t *hest;
 133
 134         /* HEST */
 135         current = acpi_align_current(current);
 136         hest = (acpi_hest_t *)current;
 137         acpi_write_hest(hest, acpi_fill_hest);
 138         acpi_add_table(rsdp, (void *)current);
 139         current += hest->header.length;
 140
 141         current = acpi_align_current(current);
 142         printk(BIOS_DEBUG, "ACPI:    * IVRS at %lx\n", current);
 143         ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
 144         if (ivrs != NULL) {
 145                 memcpy((void *)current, ivrs, ivrs->length);
 146                 ivrs = (acpi_header_t *)current;
 147                 current += ivrs->length;
 148                 acpi_add_table(rsdp, ivrs);
 149         } else {
 150                 printk(BIOS_DEBUG, "  AGESA IVRS table NULL. Skipping.\n");
 151         }
 152
 153         /* SRAT */
 154         current = acpi_align_current(current);
 155         printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
 156         srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
 157         if (srat != NULL) {
 158                 memcpy((void *)current, srat, srat->header.length);
 159                 srat = (acpi_srat_t *)current;
 160                 current += srat->header.length;
 161                 acpi_add_table(rsdp, srat);
 162         } else {
 163                 printk(BIOS_DEBUG, "  AGESA SRAT table NULL. Skipping.\n");
 164         }
 165
 166         /* SLIT */
 167         current = acpi_align_current(current);
 168         printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
 169         slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
 170         if (slit != NULL) {
 171                 memcpy((void *)current, slit, slit->header.length);
 172                 slit = (acpi_slit_t *)current;
 173                 current += slit->header.length;
 174                 acpi_add_table(rsdp, slit);
 175         } else {
 176                 printk(BIOS_DEBUG, "  AGESA SLIT table NULL. Skipping.\n");
 177         }
 178
 179         /* ALIB */
 180         current = acpi_align_current(current);
 181         printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
 182         alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
 183         if (alib != NULL) {
 184                 memcpy((void *)current, alib, alib->length);
 185                 alib = (acpi_header_t *)current;
 186                 current += alib->length;
 187                 acpi_add_table(rsdp, (void *)alib);
 188         } else {
 189                 printk(BIOS_DEBUG, "    AGESA ALIB SSDT table NULL."
 190                                                         " Skipping.\n");
 191         }
 192
 193         printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 194         return current;
 195 }
 196
 197 struct device_operations stoneyridge_northbridge_operations = {
 198         .read_resources   = read_resources,
 199         .set_resources    = set_resources,
 200         .enable_resources = pci_dev_enable_resources,
 201         .init             = northbridge_init,
 202         .acpi_fill_ssdt   = acpi_fill_root_complex_tom,
 203         .write_acpi_tables = soc_acpi_write_tables,
 204 };
 205
 206 /*
 207  * Enable VGA cycles.  Set memory ranges of the FCH legacy devices (TPM, HPET,
 208  * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted.  Set remaining
 209  * MMIO to posted.  Route all I/O to the southbridge.
 210  */
 211 void amd_initcpuio(void)
 212 {
 213         uintptr_t topmem = get_top_of_mem_below_4gb();
 214         uintptr_t base, limit;
 215
 216         /* Enable legacy video routing: D18F1xF4 VGA Enable */
 217         pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
 218
 219         /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
 220         base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
 221         limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP;
 222         pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
 223         pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
 224
 225         /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
 226         base = (topmem >> 8) | MMIO_WE | MMIO_RE;
 227         limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
 228         pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
 229         pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
 230
 231         /* Route all I/O downstream */
 232         base = 0 | IO_WE | IO_RE;
 233         limit = ALIGN_DOWN(0xffff, 4 * KiB);
 234         pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
 235         pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
 236 }
 237
 238 void fam15_finalize(void *chip_info)
 239 {
 240         u32 value;
 241
 242         /* TODO: move IOAPIC code to dsdt.asl */
 243         pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0);
 244         pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5);
 245
 246         /* disable No Snoop */
 247         value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);
 248         value &= ~HDA_NO_SNOOP_EN;
 249         pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);
 250 }
 251
 252 void domain_enable_resources(struct device *dev)
 253 {
 254         /* Must be called after PCI enumeration and resource allocation */
 255         if (!acpi_is_wakeup_s3())
 256                 do_agesawrapper(AMD_INIT_MID, "amdinitmid");
 257 }
 258
 259 void domain_read_resources(struct device *dev)
 260 {
 261         uint64_t uma_base = get_uma_base();
 262         uint32_t uma_size = get_uma_size();
 263         uint32_t mem_useable = cbmem_top();
 264         uint32_t tom = get_top_of_mem_below_4gb();
 265         uint64_t high_tom = get_top_of_mem_above_4gb();
 266         uint64_t high_mem_useable;
 267         int idx = 0x10;
 268
 269         pci_domain_read_resources(dev);
 270
 271         fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
 272
 273         /* 0x0 -> 0x9ffff */
 274         ram_range(dev, idx++, 0, 0xa0000);
 275
 276         /* 0xa0000 -> 0xbffff: legacy VGA */
 277         mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
 278
 279         /* 0xc0000 -> 0xfffff: Option ROM */
 280         reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
 281
 282         /*
 283          * 0x100000 (1MiB) -> low top usable RAM
 284          * cbmem_top() accounts for low UMA and TSEG if they are used.
 285          */
 286         ram_from_to(dev, idx++, 1 * MiB, mem_useable);
 287
 288         /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
 289         reserved_ram_from_to(dev, idx++, mem_useable, tom);
 290
 291         /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT
 292            code can find this resource */
 293         mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000);
 294
 295         /* If there is memory above 4GiB */
 296         if (high_tom >> 32) {
 297                 /* 4GiB -> high top usable */
 298                 if (uma_base >= (4ull * GiB))
 299                         high_mem_useable = uma_base;
 300                 else
 301                         high_mem_useable = high_tom;
 302
 303                 ram_from_to(dev, idx++, 4ull * GiB, high_mem_useable);
 304
 305                 /* High top usable RAM -> high top RAM */
 306                 if (uma_base >= (4ull * GiB)) {
 307                         reserved_ram_range(dev, idx++, uma_base, uma_size);
 308                 }
 309         }
 310 }
 311
 312 __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { }
 313
 314 void SetNbEnvParams(GNB_ENV_CONFIGURATION *params)
 315 {
 316         params->IommuSupport = is_dev_enabled(DEV_PTR(iommu));
 317         set_board_env_params(params);
 318 }
 319
 320 void SetNbMidParams(GNB_MID_CONFIGURATION *params)
 321 {
 322         /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */
 323         params->iGpuVgaMode = 0;
 324         params->GnbIoapicAddress = IO_APIC2_ADDR;
 325 }