soc/intel/common: Add PCIe device IDs for Snow Ridge
[coreboot2.git] / src / include / device / pci_ehci.h
blobe7a445d377c04d29c458565346c3c56d05e6dba7
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef _PCI_EHCI_H_
4 #define _PCI_EHCI_H_
6 #include <device/device.h>
7 #include <device/pci_type.h>
8 #include <stdint.h>
10 #define EHCI_BAR_INDEX 0x10
11 #define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
13 /* Return PCI BDF for an EHCI controller by a given index. PCI function
14 * must already be powered to respond to configuration requests.
16 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx);
18 u8 *pci_ehci_base_regs(pci_devfn_t dev);
19 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
21 #if !CONFIG(USBDEBUG)
22 #define pci_ehci_read_resources pci_dev_read_resources
23 #else
24 /* Relocation of EHCI Debug Port BAR
26 * PCI EHCI controller with Debug Port capability shall replace
27 * pci_dev_read_resources() with pci_ehci_read_resources() in its
28 * declaration of device_operations for .read_resources.
29 * This installs a hook to reconfigure usbdebug when resource allocator
30 * assigns a new BAR for the device.
32 struct device;
33 void pci_ehci_read_resources(struct device *dev);
34 #endif
36 #endif /* _PCI_EHCI_H_ */