soc/intel/common: Add PCIe device IDs for Snow Ridge
[coreboot2.git] / src / include / device / pnp_def.h
bloba5f2260953629ebecc866fe72e9965ba3e34f8b7
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef DEVICE_PNP_DEF_H
4 #define DEVICE_PNP_DEF_H
6 #define PNP_IDX_EN 0x30
7 #define PNP_IDX_IO0 0x60
8 #define PNP_IDX_IO1 0x62
9 #define PNP_IDX_IO2 0x64
10 #define PNP_IDX_IO3 0x66
11 #define PNP_IDX_IO4 0x68
12 #define PNP_IDX_IRQ0 0x70
13 #define PNP_IDX_IRQ1 0x72
14 #define PNP_IDX_DRQ0 0x74
15 #define PNP_IDX_DRQ1 0x75
16 #define PNP_IDX_MSC0 0xf0
17 #define PNP_IDX_MSC1 0xf1
18 #define PNP_IDX_MSC2 0xf2
19 #define PNP_IDX_MSC3 0xf3
20 #define PNP_IDX_MSC4 0xf4
21 #define PNP_IDX_MSC5 0xf5
22 #define PNP_IDX_MSC6 0xf6
23 #define PNP_IDX_MSC7 0xf7
24 #define PNP_IDX_MSC8 0xf8
25 #define PNP_IDX_MSC9 0xf9
26 #define PNP_IDX_MSCA 0xfa
27 #define PNP_IDX_MSCB 0xfb
28 #define PNP_IDX_MSCC 0xfc
29 #define PNP_IDX_MSCD 0xfd
30 #define PNP_IDX_MSCE 0xfe
31 #define PNP_IDX_RSVD 0xff
33 #endif /* DEVICE_PNP_DEF_H */