cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / amd / chausie / Makefile.mk
bloba5954362cedd7b5ef5636a1d7b52c26b0618747f
1 # SPDX-License-Identifier: GPL-2.0-only
3 bootblock-y += bootblock.c
4 bootblock-y += early_gpio.c
5 bootblock-y += ec.c
7 romstage-y += port_descriptors.c
9 ramstage-y += chromeos.c
10 ramstage-y += gpio.c
11 ramstage-y += port_descriptors.c
13 ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6.bin),)
14 APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6.bin
15 APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_DefaultRecovery.bin
16 else
17 show_notices:: warn_no_apcb
18 endif
20 ifeq ($(CONFIG_CHAUSIE_HAVE_MCHP_FW),y)
21 $(call add_intermediate, add_mchp_fw)
22 $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_CHAUSIE_MCHP_SIG_FILE) --fill-upward
24 # calculate the absolute position from the config offset
25 CHAUSIE_EC_POSITION=$(call int-add, \
26 $(call int-subtract, 0xffffffff \
27 $(CONFIG_ROM_SIZE)) $(CONFIG_CHAUSIE_MCHP_FW_OFFSET) 1)
29 cbfs-files-y += ec/ecfw
30 ec/ecfw-file := $(CONFIG_CHAUSIE_MCHP_FW_FILE)
31 ec/ecfw-position := $(CHAUSIE_EC_POSITION)
32 ec/ecfw-type := raw
34 else
35 show_notices:: warn_no_mchp
36 endif # CONFIG_CHAUSIE_HAVE_MCHP_FW
38 PHONY+=warn_no_mchp
39 warn_no_mchp:
40 printf "\n\t** WARNING **\n"
41 printf "coreboot has been built without the Microchip EC FW.\n"
42 printf "Do not flash this image. Your Chausie's power button\n"
43 printf "will not respond when you press it.\n\n"