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HEAD
cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git]
/
src
/
mainboard
/
google
/
brya
/
chromeos-nissa-16MiB-debugfsp.fmd
blob
205f3dd1e541722c1f57507f12d7ac04b198ee43
1
FLASH 16M {
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SI_ALL 3712K {
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SI_DESC 4K
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SI_ME
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}
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SI_BIOS 12672K {
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RW_SECTION_A 4212K {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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}
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RW_MISC 152K {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 64K
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}
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 4K {
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SHARED_DATA 4K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 8K
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}
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RW_SECTION_B 4212K {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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}
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO 4M {
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RO_VPD(PRESERVE) 16K
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RO_GSCVD 8K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 12K
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COREBOOT(CBFS)
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}
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}
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}
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}