src/mainboard/google/brya/variants/agah/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A7  : SRCCLK_OE7# ==> LAN_WAKE_ODL */
  11         PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE),
  12         /* A8  : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */
  13         PAD_NC(GPP_A8, NONE),
  14         /* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */
  15         PAD_CFG_GPO(GPP_A12, 1, DEEP),
  16         /* A14 : USB_OC1# ==> USB_C0_OC_ODL */
  17         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  18         /* A15 : USB_OC2# ==> USB_C2_OC_ODL */
  19         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  20         /* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */
  21         PAD_CFG_GPI(GPP_A17, NONE, PLTRST),
  22         /* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */
  23         PAD_CFG_GPO(GPP_A19, 1, PLTRST),
  24         /* A20 : DDSP_HPD2 ==> NC */
  25         PAD_NC(GPP_A20, NONE),
  26         /* A21 : DDPC_CTRCLK ==> EN_PP3300_GPU_X */
  27         PAD_CFG_GPO(GPP_A21, 0, PLTRST),
  28         /* A22 : DDPC_CTRCLK ==> PG_PP3300_GPU_X_OD */
  29         PAD_CFG_GPI(GPP_A22, NONE, DEEP),
  30
  31         /* B3  : PROC_GP2 ==> GPU_PERST_L */
  32         PAD_CFG_GPO(GPP_B3, 0, PLTRST),
  33         /* B5  : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */
  34         PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
  35         /* B6  : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */
  36         PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
  37         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  38         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  39         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
  40         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  41         /* B15  : TIME_SYNC0 ==> NC */
  42         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  43
  44         /* C0  : SMBCLK ==> NC */
  45         PAD_NC(GPP_C0, NONE),
  46         /* C1  : SMBDATA ==> NC */
  47         PAD_NC(GPP_C1, NONE),
  48         /* C3 : SML0CLK ==> NC */
  49         PAD_NC(GPP_C3, NONE),
  50         /* C4 : SML0DATA ==> NC */
  51         PAD_NC(GPP_C4, NONE),
  52         /* C6  : SML1CLK ==> NC */
  53         PAD_NC(GPP_C6, NONE),
  54         /* C7  : SML1DATA ==> NC */
  55         PAD_NC(GPP_C7, NONE),
  56
  57         /* D0  : ISH_GP0 ==> NC */
  58         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  59         /* D1  : ISH_GP1 ==> NC */
  60         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  61         /* D2  : ISH_GP2 ==> LAN_PE_ISOLATE_ODL */
  62         PAD_CFG_GPO(GPP_D2, 1, DEEP),
  63         /* D3 : ISH_GP3 ==> NC */
  64         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  65         /* D5  : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */
  66         PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1),
  67         /* D9  : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */
  68         PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
  69         /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
  70         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  71         /* D13 : ISH_UART0_RXD ==> NC */
  72         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  73         /* D15 : ISH_UART0_RTS# ==> NC */
  74         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  75         /* D16 : ISH_UART0_CTS# ==> NC */
  76         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  77
  78         /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X */
  79         PAD_CFG_GPO(GPP_E0, 0, DEEP),
  80         /* E3  : PROC_GP0 ==> PG_PPVAR_GPU_NVVDD_X_OD (board rev 3 and later) */
  81         PAD_CFG_GPI(GPP_E3, NONE, DEEP),
  82         /* E4  : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */
  83         PAD_CFG_GPI(GPP_E4, NONE, DEEP),
  84         /* E5  : SATA_DEVSLP1 ==> PG_GPU_ALLRAILS */
  85         PAD_CFG_GPO(GPP_E5, 0, PLTRST),
  86         /* E7  : PROC_GP1 ==> NC */
  87         PAD_NC(GPP_E7, NONE),
  88         /* E9  : USB_OC0# ==> USB_A2_OC_ODL */
  89         PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
  90         /* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */
  91         PAD_CFG_GPO(GPP_E10, 0, PLTRST),
  92         /* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD (before board rev 3) */
  93         PAD_CFG_GPI(GPP_E16, NONE, DEEP),
  94         /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */
  95         PAD_CFG_GPI(GPP_E17, NONE, DEEP),
  96         /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */
  97         PAD_CFG_GPO_LOCK(GPP_E18, 0, LOCK_CONFIG),
  98         /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
  99         PAD_NC(GPP_E19, NONE),
 100         /* E20 : DDP2_CTRLCLK ==> PG_PP1800_GPU_X_OD */
 101         PAD_CFG_GPI(GPP_E20, NONE, DEEP),
 102         /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
 103         PAD_NC(GPP_E21, NONE),
 104
 105         /* F6  : CNV_PA_BLANKING ==> NC */
 106         PAD_NC(GPP_F6, NONE),
 107         /* F11 : THC1_SPI2_CLK ==> NC */
 108         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 109         /* F12 : GSXDOUT ==> EN_PP0950_GPU_X (board rev 3 and after) */
 110         PAD_CFG_GPO(GPP_F12, 0, PLTRST),
 111         /* F13 : GSXDOUT ==> NC */
 112         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 113         /* F14 : GSXDIN ==> TCHPAD_INT_ODL */
 114         PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT),
 115         /* F15 : GSXSRESET# ==> NC */
 116         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 117         /* F16 : GSXCLK ==> NC */
 118         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 119         /* F19 : SRCCLKREQ6# ==> NC */
 120         PAD_NC(GPP_F19, NONE),
 121         /* F20 : EXT_PWR_GATE# ==> NC */
 122         PAD_NC(GPP_F20, NONE),
 123         /* F21 : EXT_PWR_GATE2# ==> NC */
 124         PAD_NC(GPP_F21, NONE),
 125
 126         /* H6  : I2C1_SDA ==> PCH_I2C_GPU_SDA */
 127         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 128         /* H7  : I2C1_SCL ==> PCH_I2C_GPU_SCL */
 129         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 130         /* H8  : I2C4_SDA ==> NC */
 131         PAD_NC(GPP_H8, NONE),
 132         /* H9  : I2C4_SCL ==> NC */
 133         PAD_NC(GPP_H9, NONE),
 134         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 135         PAD_CFG_GPO(GPP_H13, 1, PLTRST),
 136         /* H19 : SRCCLKREQ4# ==> LAN_CLKREQ_ODL */
 137         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 138         /* H21 : IMGCLKOUT2 ==> NC */
 139         PAD_NC(GPP_H21, NONE),
 140         /* H22 : IMGCLKOUT3 ==> NC */
 141         PAD_NC(GPP_H22, NONE),
 142
 143         /* R4 : HDA_RST# ==> DMIC_CLK0 */
 144         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 145         /* R5 : HDA_SDI1 ==> DMIC_DATA0 */
 146         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 147         /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
 148         PAD_NC(GPP_R6, NONE),
 149         /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
 150         PAD_NC(GPP_R7, NONE),
 151
 152         /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK */
 153         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 154         /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM */
 155         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 156         /* S2 : SNDW1_CLK ==> I2S_PCH_SPKR_RX */
 157         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 158         /* S3 : SNDW1_DATA ==> I2S_PCH_SPKR_TX */
 159         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
 160         /* S6 : SNDW3_CLK ==> SDW_HP_CLK */
 161         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
 162         /* S7 : SNDW3_DATA ==> SDW_HP_DATA */
 163         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
 164 };
 165
 166 /* Early pad configuration in bootblock */
 167 static const struct pad_config early_gpio_table[] = {
 168         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 169         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 170         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
 171         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 172         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
 173         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 174         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 175         PAD_CFG_GPO(GPP_D11, 1, PLTRST),
 176         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 177         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 178         /* E15 : RSVD_TP ==> PCH_WP_OD */
 179         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 180         /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */
 181         PAD_CFG_GPO(GPP_E18, 0, PLTRST),
 182         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 183         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 184         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 185         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 186         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 187         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 188         /*
 189          * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
 190          * then deassert PERST# in romstage
 191          */
 192         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 193         PAD_CFG_GPO(GPP_H13, 1, PLTRST),
 194         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 195         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 196
 197         /* CPU PCIe VGPIO for PEG60 */
 198         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 199         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 200         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 201         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 202         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 203         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 204         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 205         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 206         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 207         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 208         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 209         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 210         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 211         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 212         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 213         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 214         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 215         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 216         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 217         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 218 };
 219
 220 static const struct pad_config romstage_gpio_table[] = {
 221         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 222         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 223 };
 224
 225 const struct pad_config *variant_gpio_override_table(size_t *num)
 226 {
 227         *num = ARRAY_SIZE(override_gpio_table);
 228         return override_gpio_table;
 229 }
 230
 231 const struct pad_config *variant_early_gpio_table(size_t *num)
 232 {
 233         *num = ARRAY_SIZE(early_gpio_table);
 234         return early_gpio_table;
 235 }
 236
 237 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 238 {
 239         *num = ARRAY_SIZE(romstage_gpio_table);
 240         return romstage_gpio_table;
 241 }