src/mainboard/google/brya/variants/anahera4es/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A7  : SRCCLK_OE7# ==> NC */
  11         PAD_NC(GPP_A7, NONE),
  12         /* A17 : DISP_MISCC ==> NC */
  13         PAD_NC(GPP_A17, NONE),
  14         /* A19 : DDSP_HPD1 ==> NC */
  15         PAD_NC(GPP_A19, NONE),
  16         /* A20 : DDSP_HPD2 ==> NC */
  17         PAD_NC(GPP_A20, NONE),
  18         /* A21 : DDPC_CTRCLK ==> NC */
  19         PAD_NC(GPP_A21, NONE),
  20         /* A22 : DDPC_CTRLDATA ==> NC */
  21         PAD_NC(GPP_A22, NONE),
  22
  23         /* B3  : PROC_GP2 ==> eMMC_PERST_L */
  24         PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
  25         /* B5  : ISH_I2C0_SDA ==> NC */
  26         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  27         /* B6  : ISH_I2C0_SCL ==> NC */
  28         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  29         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  30         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  31         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  32         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  33         /* B15  : TIME_SYNC0 ==> NC */
  34         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  35
  36         /* C3 : SML0CLK ==> NC */
  37         PAD_NC(GPP_C3, NONE),
  38         /* C4 : SML0DATA ==> NC */
  39         PAD_NC(GPP_C4, NONE),
  40
  41         /* D3  : ISH_GP3 ==> NC */
  42         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  43         /* D5  : SRCCLKREQ0# ==> NC */
  44         PAD_NC(GPP_D5, NONE),
  45         /* D7  : SRCCLKREQ2# ==> NC */
  46         PAD_NC(GPP_D7, NONE),
  47         /* D13 : ISH_UART0_RXD ==> NC */
  48         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  49         /* D14 : ISH_UART0_TXD ==> NC */
  50         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
  51         /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
  52         PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
  53         /* D16 : ISH_UART0_CTS# ==> NC */
  54         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  55         /* D17 : UART1_RXD ==> NC */
  56         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  57
  58         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L */
  59         PAD_CFG_GPO(GPP_E0, 1, PLTRST),
  60         /* E3  : PROC_GP0 ==> NC */
  61         PAD_NC(GPP_E3, NONE),
  62         /* E7  : PROC_GP1 ==> NC */
  63         PAD_NC(GPP_E7, NONE),
  64         /* E16 : RSVD_TP ==> WWAN_RST_L */
  65         PAD_CFG_GPO(GPP_E16, 1, DEEP),
  66         /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
  67         PAD_CFG_GPO(GPP_E20, 1, DEEP),
  68         /* E22 : DDPA_CTRLCLK ==> SC_PWR_SV */
  69         PAD_CFG_GPO(GPP_E22, 1, DEEP),
  70         /* E23 : DDPA_CTRLDATA ==> NC */
  71         PAD_NC(GPP_E23, NONE),
  72
  73         /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
  74         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
  75         /* F20 : EXT_PWR_GATE# ==> NC */
  76         PAD_NC(GPP_F20, NONE),
  77
  78         /* H20 : IMGCLKOUT1 ==> NC */
  79         PAD_NC(GPP_H20, NONE),
  80         /* H21 : IMGCLKOUT2 ==> Privacy screen */
  81         PAD_CFG_GPO(GPP_H21, 0, DEEP),
  82         /* H22 : IMGCLKOUT3 ==> NC */
  83         PAD_NC(GPP_H22, NONE),
  84         /* H23 : SRCCLKREQ5# ==> NC */
  85         PAD_NC(GPP_H23, NONE),
  86
  87         /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
  88         PAD_NC(GPP_R6, NONE),
  89         /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
  90         PAD_NC(GPP_R7, NONE),
  91
  92         /* S4 : SNDW2_CLK ==> NC */
  93         PAD_NC(GPP_S4, NONE),
  94         /* S5 : SNDW2_DATA ==> NC */
  95         PAD_NC(GPP_S5, NONE),
  96         /* S6 : SNDW3_CLK ==> NC */
  97         PAD_NC(GPP_S6, NONE),
  98         /* S7 : SNDW3_DATA ==> NC */
  99         PAD_NC(GPP_S7, NONE),
 100         /*
 101          * E0 : SATAXPCIE0 ==> WWAN_PERST_L
 102          * Drive high here, so that PERST_L is sequenced after RST_L
 103          */
 104         PAD_CFG_GPO(GPP_E0, 1, DEEP),
 105 };
 106
 107 /* Early pad configuration in bootblock */
 108 static const struct pad_config early_gpio_table[] = {
 109         /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
 110         PAD_CFG_GPO(GPP_A12, 1, DEEP),
 111         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 112         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 113         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
 114         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 115         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
 116         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 117         /*
 118          * D1  : ISH_GP1 ==> FP_RST_ODL
 119          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 120          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 121          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 122          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 123          * FPMCU not working after a S3 resume. This is a known issue.
 124          */
 125         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 126         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 127         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 128         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 129         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 130         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L */
 131         PAD_CFG_GPO(GPP_E0, 0, DEEP),
 132         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 133         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 134         /* E15 : RSVD_TP ==> PCH_WP_OD */
 135         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 136         /* E16 : RSVD_TP ==> WWAN_RST_L  */
 137         PAD_CFG_GPO(GPP_E16, 0, DEEP),
 138         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 139         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 140         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
 141         PAD_CFG_GPO(GPP_F21, 0, DEEP),
 142         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 143         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 144         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 145         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 146         /*
 147          * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
 148          * then deassert PERST# in romstage
 149          */
 150         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 151         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 152         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 153         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 154         /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */
 155         PAD_CFG_GPO(GPP_E20, 1, DEEP),
 156 };
 157
 158 static const struct pad_config romstage_gpio_table[] = {
 159         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 160         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 161
 162         /* Enable touchscreen, hold in reset */
 163         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 164         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 165         /* C1  : SMBDATA ==> USI_RST_L */
 166         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 167
 168         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 169         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 170         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 171         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 172
 173         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 174         PAD_CFG_GPO(GPP_F21, 1, DEEP),
 175 };
 176
 177 const struct pad_config *variant_gpio_override_table(size_t *num)
 178 {
 179         *num = ARRAY_SIZE(override_gpio_table);
 180         return override_gpio_table;
 181 }
 182
 183 const struct pad_config *variant_early_gpio_table(size_t *num)
 184 {
 185         *num = ARRAY_SIZE(early_gpio_table);
 186         return early_gpio_table;
 187 }
 188
 189 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 190 {
 191         *num = ARRAY_SIZE(romstage_gpio_table);
 192         return romstage_gpio_table;
 193 }