src/mainboard/google/brya/variants/brask/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Early pad configuration in bootblock */
   9 static const struct pad_config early_gpio_table[] = {
  10         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  11         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  12         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  13         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  14         /*
  15          * D1  : ISH_GP1 ==> FP_RST_ODL
  16          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
  17          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
  18          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
  19          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
  20          * FPMCU not working after a S3 resume. This is a known issue.
  21          */
  22         PAD_CFG_GPO(GPP_D1, 0, DEEP),
  23         /* D2  : ISH_GP2 ==> EN_FP_PWR */
  24         PAD_CFG_GPO(GPP_D2, 1, DEEP),
  25         /* E15 : RSVD_TP ==> PCH_WP_OD */
  26         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
  27         /* F14 : GSXDIN ==> EN_PP3300_SSD */
  28         PAD_CFG_GPO(GPP_F14, 1, DEEP),
  29         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  30         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  31         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  32         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
  33         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  34         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
  35         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
  36         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  37         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
  38         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  39         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
  40         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  41
  42         /* CPU PCIe VGPIO for PEG60 */
  43         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
  44         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
  45         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
  46         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
  47         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
  48         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
  49         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
  50         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
  51         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
  52         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
  53         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
  54         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
  55         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
  56         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
  57         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
  58         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
  59         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
  60         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
  61         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
  62         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
  63 };
  64
  65 static const struct pad_config romstage_gpio_table[] = {
  66         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  67         PAD_CFG_GPO(GPP_B4, 1, DEEP),
  68
  69         /* D1  : ISH_GP1 ==> FP_RST_ODL */
  70         PAD_CFG_GPO(GPP_D1, 0, DEEP),
  71         /* D2  : ISH_GP2 ==> EN_FP_PWR */
  72         PAD_CFG_GPO(GPP_D2, 0, DEEP),
  73 };
  74
  75 const struct pad_config *variant_early_gpio_table(size_t *num)
  76 {
  77         *num = ARRAY_SIZE(early_gpio_table);
  78         return early_gpio_table;
  79 }
  80
  81 const struct pad_config *variant_romstage_gpio_table(size_t *num)
  82 {
  83         *num = ARRAY_SIZE(romstage_gpio_table);
  84         return romstage_gpio_table;
  85 }