?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / brya / variants / constitution / overridetree.cb
blobc6083f13876a3fc778a30119f8d0a4925711a599
1 fw_config
2 field WIFI_SAR_ID 30 31
3 option ID_0 0
4 option UNUSED 3
5 end
6 end
7
8 chip soc/intel/alderlake
9 register "domain_vr_config[VR_DOMAIN_IA]" = "{
10 .enable_fast_vmode = 1,
11 }"
12
13 register "sagv" = "SaGv_Enabled"
14
15 # SOC Aux orientation override:
16 # This is a bitfield that corresponds to up to 4 TCSS ports.
17 # Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2, Bits (4,5)for TCSS Port3.
18 # TcssAuxOri = 010100b
19 # Bit0,Bit2,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
20 # Bit1,Bit3,Bit5 set to "0" indicates Aux lines are not swapped on the
21 # motherboard to USBC connector
22 register "tcss_aux_ori" = "0x14"
23
24 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
25 register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A19, .pad_auxn_dc = GPP_A20}"
26
27 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # HDMI-IN
28 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
29 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
30 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
31
32 register "usb3_ports[0]" = "{
33 .enable = 1,
34 .ocpin = OC_SKIP,
35 .tx_de_emp = 0x2B,
36 .tx_downscale_amp = 0x00,
37 }" # Type-A port A0
38 register "usb3_ports[1]" = "{
39 .enable = 1,
40 .ocpin = OC_SKIP,
41 .tx_de_emp = 0x2B,
42 .tx_downscale_amp = 0x00,
43 }" # Type-A port A1
44
45 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI-IN
46 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port A3
47
48 register "serial_io_gspi_mode" = "{
49 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
50 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
51 }"
52
53 register "ddi_ports_config" = "{
54 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
55 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
56 [DDI_PORT_1] = DDI_ENABLE_HPD,
57 [DDI_PORT_3] = DDI_ENABLE_HPD,
58 [DDI_PORT_4] = DDI_ENABLE_HPD,
59 }"
60
61 device domain 0 on
62 device ref dtt on
63 chip drivers/intel/dptf
64 ## sensor information
65 register "options.tsr[0].desc" = ""DRAM""
66 register "options.tsr[1].desc" = ""Charger""
67
68 # TODO: below values are initial reference values only
69 ## Active Policy
70 register "policies.active" = "{
71 [0] = {
72 .target = DPTF_CPU,
73 .thresholds = {
74 TEMP_PCT(85, 90),
75 TEMP_PCT(80, 80),
76 TEMP_PCT(75, 70),
77 }
78 }
79 }"
80
81 ## Passive Policy
82 register "policies.passive" = "{
83 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
84 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
85 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
86 }"
87
88 ## Critical Policy
89 register "policies.critical" = "{
90 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
91 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
92 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
93 }"
94
95 register "controls.power_limits" = "{
96 .pl1 = {
97 .min_power = 3000,
98 .max_power = 15000,
99 .time_window_min = 28 * MSECS_PER_SEC,
100 .time_window_max = 32 * MSECS_PER_SEC,
101 .granularity = 200,
102 },
103 .pl2 = {
104 .min_power = 55000,
105 .max_power = 55000,
106 .time_window_min = 28 * MSECS_PER_SEC,
107 .time_window_max = 32 * MSECS_PER_SEC,
108 .granularity = 1000,
109 }
110 }"
111
112 ## Charger Performance Control (Control, mA)
113 register "controls.charger_perf" = "{
114 [0] = { 255, 1700 },
115 [1] = { 24, 1500 },
116 [2] = { 16, 1000 },
117 [3] = { 8, 500 }
118 }"
119
120 ## Fan Performance Control (Percent, Speed, Noise, Power)
121 register "controls.fan_perf" = "{
122 [0] = { 90, 6700, 220, 2200, },
123 [1] = { 80, 5800, 180, 1800, },
124 [2] = { 70, 5000, 145, 1450, },
125 [3] = { 60, 4900, 115, 1150, },
126 [4] = { 50, 3838, 90, 900, },
127 [5] = { 40, 2904, 55, 550, },
128 [6] = { 30, 2337, 30, 300, },
129 [7] = { 20, 1608, 15, 150, },
130 [8] = { 10, 800, 10, 100, },
131 [9] = { 0, 0, 0, 50, }
132 }"
133
134 ## Fan options
135 register "options.fan.fine_grained_control" = "1"
136 register "options.fan.step_size" = "2"
137
138 device generic 0 alias dptf_policy on end
139 end
140 end
141 device ref pcie4_0 on
142 # Enable CPU PCIE RP 1 using CLK 0
143 register "cpu_pcie_rp[CPU_RP(1)]" = "{
144 .clk_req = 0,
145 .clk_src = 0,
146 .flags = PCIE_RP_LTR | PCIE_RP_AER,
147 }"
148 end
149 device ref tcss_dma0 on
150 chip drivers/intel/usb4/retimer
151 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
152 use tcss_usb3_port1 as dfp[0].typec_port
153 device generic 0 on end
154 end
155 end
156 device ref cnvi_wifi on
157 chip drivers/wifi/generic
158 register "wake" = "GPE0_PME_B0"
159 device generic 0 on end
160 end
161 end
162 device ref pcie_rp6 on
163 # Enable PCIE 6 using clk 3
164 register "pch_pcie_rp[PCH_RP(6)]" = "{
165 .clk_src = 3,
166 .clk_req = 3,
167 .flags = PCIE_RP_LTR | PCIE_RP_AER,
168 }"
169 end #TPU0
170 device ref pcie_rp7 on
171 # Enable PCIE 7 using clk 6
172 register "pch_pcie_rp[PCH_RP(7)]" = "{
173 .clk_src = 6,
174 .clk_req = 6,
175 .flags = PCIE_RP_LTR | PCIE_RP_AER,
176 }"
177 chip drivers/net
178 register "wake" = "GPE0_DW0_07"
179 register "led_feature" = "0xe0"
180 register "customized_led0" = "0x23f"
181 register "customized_led2" = "0x028"
182 register "enable_aspm_l1_2" = "1"
183 register "add_acpi_dma_property" = "true"
184 device pci 00.0 on end
185 end
186 end # RTL8125 Ethernet NIC
187 device ref pcie_rp8 on
188 # Enable PCIE 8 using clk 4
189 register "pch_pcie_rp[PCH_RP(8)]" = "{
190 .clk_src = 4,
191 .clk_req = 4,
192 .flags = PCIE_RP_LTR | PCIE_RP_AER,
193 }"
194 end #TPU1
195 device ref pcie_rp9 on
196 # Enable PCIE 9 using clk 5
197 register "pch_pcie_rp[PCH_RP(9)]" = "{
198 .clk_src = 5,
199 .clk_req = 5,
200 .flags = PCIE_RP_LTR | PCIE_RP_AER,
201 }"
202 end # I350
203 device ref gspi1 off end
204 device ref pch_espi on
205 chip ec/google/chromeec
206 use conn0 as mux_conn[0]
207 use conn1 as mux_conn[1]
208 use conn2 as mux_conn[2]
209 device pnp 0c09.0 on end
210 end
211 end
212 device ref pmc hidden
213 chip drivers/intel/pmc_mux
214 device generic 0 on
215 chip drivers/intel/pmc_mux/conn
216 use usb2_port1 as usb2_port
217 use tcss_usb3_port1 as usb3_port
218 device generic 0 alias conn0 on end
219 end
220 chip drivers/intel/pmc_mux/conn
221 use usb2_port2 as usb2_port
222 use tcss_usb3_port2 as usb3_port
223 device generic 1 alias conn1 on end
224 end
225 chip drivers/intel/pmc_mux/conn
226 use usb2_port3 as usb2_port
227 use tcss_usb3_port3 as usb3_port
228 device generic 2 alias conn2 on end
229 end
230 end
231 end
232 end
233 device ref tcss_xhci on
234 chip drivers/usb/acpi
235 device ref tcss_root_hub on
236 chip drivers/usb/acpi
237 register "desc" = ""USB3 Type-C Port C0 (MLB)""
238 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
239 register "use_custom_pld" = "true"
240 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
241 device ref tcss_usb3_port1 on end
242 end
243 chip drivers/usb/acpi
244 register "desc" = ""USB3 Type-C Port C1 (MLB)""
245 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
246 register "use_custom_pld" = "true"
247 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
248 device ref tcss_usb3_port2 on end
249 end
250 chip drivers/usb/acpi
251 register "desc" = ""USB3 Type-C Port C2 (MLB)""
252 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
253 register "use_custom_pld" = "true"
254 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))"
255 device ref tcss_usb3_port3 on end
256 end
257 end
258 end
259 end
260 device ref xhci on
261 chip drivers/usb/acpi
262 device ref xhci_root_hub on
263 chip drivers/usb/acpi
264 register "desc" = ""USB2 Type-C Port C0 (MLB)""
265 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
266 register "use_custom_pld" = "true"
267 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
268 device ref usb2_port1 on end
269 end
270 chip drivers/usb/acpi
271 register "desc" = ""USB2 Type-C Port C1 (MLB)""
272 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
273 register "use_custom_pld" = "true"
274 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
275 device ref usb2_port2 on end
276 end
277 chip drivers/usb/acpi
278 register "desc" = ""USB2 Type-C Port C2 (MLB)""
279 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
280 register "use_custom_pld" = "true"
281 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))"
282 device ref usb2_port3 on end
283 end
284 chip drivers/usb/acpi
285 register "desc" = ""USB2 Type-A Port HDMI-to-USB""
286 register "type" = "UPC_TYPE_INTERNAL"
287 device ref usb2_port4 on end
288 end
289 chip drivers/usb/acpi
290 register "desc" = ""USB2 Type-A Port A1 (MLB)""
291 register "type" = "UPC_TYPE_A"
292 register "use_custom_pld" = "true"
293 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
294 device ref usb2_port8 on end
295 end
296 chip drivers/usb/acpi
297 register "desc" = ""USB2 Type-A Port A0 (MLB)""
298 register "type" = "UPC_TYPE_A"
299 register "use_custom_pld" = "true"
300 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, RIGHT, ACPI_PLD_GROUP(4, 2))"
301 device ref usb2_port9 on end
302 end
303 chip drivers/usb/acpi
304 register "desc" = ""USB2 Bluetooth""
305 register "type" = "UPC_TYPE_INTERNAL"
306 register "reset_gpio" =
307 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
308 device ref usb2_port10 on end
309 end
310 chip drivers/usb/acpi
311 register "desc" = ""USB3 Type-A Port A0 (MLB)""
312 register "type" = "UPC_TYPE_USB3_A"
313 register "use_custom_pld" = "true"
314 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, RIGHT, ACPI_PLD_GROUP(4, 2))"
315 device ref usb3_port1 on end
316 end
317 chip drivers/usb/acpi
318 register "desc" = ""USB3 Type-A Port A1 (MLB)""
319 register "type" = "UPC_TYPE_USB3_A"
320 register "use_custom_pld" = "true"
321 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
322 device ref usb3_port2 on end
323 end
324 chip drivers/usb/acpi
325 register "desc" = ""USB3 M.2 HDMI-to-USB""
326 register "type" = "UPC_TYPE_INTERNAL"
327 device ref usb3_port3 on end
328 end
329 end
330 end
331 end
332 end
333 end
coreboot repo mirror