1 chip soc
/intel
/alderlake
3 register
"usb2_ports[2]" = "USB2_PORT_EMPTY"
4 register
"usb2_ports[3]" = "USB2_PORT_EMPTY"
5 register
"usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # UFCamera
7 register
"usb3_ports[2]" = "USB3_PORT_EMPTY"
8 register
"usb3_ports[3]" = "USB3_PORT_EMPTY"
10 register
"tcss_ports[2]" = "TCSS_PORT_EMPTY"
12 register
"serial_io_i2c_mode" = "{
13 [PchSerialIoIndexI2C0] = PchSerialIoPci,
14 [PchSerialIoIndexI2C1] = PchSerialIoPci,
15 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
16 [PchSerialIoIndexI2C3] = PchSerialIoPci,
17 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
18 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
21 register
"serial_io_gspi_mode" = "{
22 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
23 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
26 # Enable eDP in Port A
27 register
"ddi_portA_config" = "1"
29 register
"ddi_ports_config" = "{
30 [DDI_PORT_A] = DDI_ENABLE_HPD,
31 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
34 register
"sagv" = "SaGv_Enabled"
36 # Intel Common SoC Config
37 #
+-------------------+---------------------------+
39 #
+-------------------+---------------------------+
41 #| I2C1 | cr50 TPM. Early init is |
42 #| | required
to set up a BAR |
43 #| |
for TPM communication |
44 #| I2C3 | TouchScreen |
45 #
+-------------------+---------------------------+
46 register
"common_soc_config" = "{
48 .speed = I2C_SPEED_FAST,
52 .speed = I2C_SPEED_FAST,
55 .data_hold_time_ns = 50,
58 .speed = I2C_SPEED_FAST,
61 .data_hold_time_ns = 50,
67 # Enable CPU PCIE RP
1 using CLK
0
68 register
"cpu_pcie_rp[CPU_RP(1)]" = "{
71 .flags = PCIE_RP_LTR | PCIE_RP_AER,
74 device ref tcss_xhci on
76 device ref tcss_root_hub on
78 register
"desc" = ""USB3
Type-C Port C0
(MLB
)""
79 register
"type" = "UPC_TYPE_C_USB2_SS_SWITCH"
80 register
"use_custom_pld" = "true"
81 register
"custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
82 register
"usb_lpm_incapable" = "true"
83 device ref tcss_usb3_port1 on
end
86 register
"desc" = ""USB3
Type-C Port C1
(MLB
)""
87 register
"type" = "UPC_TYPE_C_USB2_SS_SWITCH"
88 register
"use_custom_pld" = "true"
89 register
"custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
90 register
"usb_lpm_incapable" = "true"
91 device ref tcss_usb3_port2 on
end
98 device ref xhci_root_hub on
100 register
"desc" = ""USB2
Type-C Port C0
(MLB
)""
101 register
"type" = "UPC_TYPE_C_USB2_SS_SWITCH"
102 register
"use_custom_pld" = "true"
103 register
"custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 1))"
104 device ref usb2_port1 on
end
106 chip drivers
/usb
/acpi
107 register
"desc" = ""USB2
Type-C Port C1
(MLB
)""
108 register
"type" = "UPC_TYPE_C_USB2_SS_SWITCH"
109 register
"use_custom_pld" = "true"
110 register
"custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))"
111 device ref usb2_port2 on
end
113 chip drivers
/usb
/acpi
114 register
"desc" = ""UFCamera
""
115 register
"type" = "UPC_TYPE_INTERNAL"
116 register
"has_power_resource" = "1"
117 register
"enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A17)"
118 register
"enable_delay_ms" = "20"
119 device ref usb2_port5 on
end
121 chip drivers
/usb
/acpi
122 register
"desc" = ""USB2
Type-A Port A3
(MLB
)""
123 register
"type" = "UPC_TYPE_A"
124 register
"use_custom_pld" = "true"
125 register
"custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
126 device ref usb2_port6 on
end
128 chip drivers
/usb
/acpi
129 register
"desc" = ""USB2
Type-A Port A2
(MLB
)""
130 register
"type" = "UPC_TYPE_A"
131 register
"use_custom_pld" = "true"
132 register
"custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))"
133 device ref usb2_port7 on
end
135 chip drivers
/usb
/acpi
136 register
"desc" = ""USB2
Type-A Port A1
(MLB
)""
137 register
"type" = "UPC_TYPE_A"
138 register
"use_custom_pld" = "true"
139 register
"custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))"
140 device ref usb2_port8 on
end
142 chip drivers
/usb
/acpi
143 register
"desc" = ""USB2
Type-A Port A0
(MLB
)""
144 register
"type" = "UPC_TYPE_A"
145 register
"use_custom_pld" = "true"
146 register
"custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
147 device ref usb2_port9 on
end
149 chip drivers
/usb
/acpi
150 register
"desc" = ""USB2 Bluetooth
""
151 register
"type" = "UPC_TYPE_INTERNAL"
152 register
"reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
153 device ref usb2_port10 on
end
155 chip drivers
/usb
/acpi
156 register
"desc" = ""USB3
Type-A Port A0
(MLB
)""
157 register
"type" = "UPC_TYPE_USB3_A"
158 register
"use_custom_pld" = "true"
159 register
"custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
160 device ref usb3_port1 on
end
162 chip drivers
/usb
/acpi
163 register
"desc" = ""USB3
Type-A Port A1
(MLB
)""
164 register
"type" = "UPC_TYPE_USB3_A"
165 register
"use_custom_pld" = "true"
166 register
"custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 1))"
167 device ref usb3_port2 on
end
173 chip drivers
/i2c
/nau8825
174 register
"irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
175 register
"jkdet_enable" = "1"
176 register
"jkdet_pull_enable" = "0"
177 register
"jkdet_pull_up" = "0"
178 register
"jkdet_polarity" = "1" # ActiveLow
179 register
"vref_impedance" = "2" #
125kOhm
180 register
"micbias_voltage" = "6" #
2.754
181 register
"sar_threshold_num" = "4"
182 register
"sar_threshold[0]" = "0x0C"
183 register
"sar_threshold[1]" = "0x1C"
184 register
"sar_threshold[2]" = "0x38"
185 register
"sar_threshold[3]" = "0x60"
186 register
"sar_hysteresis" = "1"
187 register
"sar_voltage" = "6"
188 register
"sar_compare_time" = "0" #
500ns
189 register
"sar_sampling_time" = "0" #
2us
190 register
"short_key_debounce" = "2" #
100ms
191 register
"jack_insert_debounce" = "7" #
512ms
192 register
"jack_eject_debounce" = "7" #
512ms
198 register
"generic.hid" = ""LM230001
""
199 register
"generic.desc" = ""LM238 Touchscreen
""
200 register
"generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
201 register
"generic.detect" = "1"
202 register
"generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
203 register
"generic.enable_delay_ms" = "6"
204 register
"generic.has_power_resource" = "1"
208 device ref pcie_rp5 on
209 # Enable PCIE
5 using clk
2
210 register
"pch_pcie_rp[PCH_RP(5)]" = "{
213 .flags = PCIE_RP_LTR | PCIE_RP_AER,
215 chip soc
/intel
/common
/block
/pcie
/rtd3
216 register
"enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
217 register
"reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
218 register
"srcclk_pin" = "2"
219 device generic
0 on
end
222 device ref pcie_rp7 on
223 # Enable PCIE
7 using clk
6
224 register
"pch_pcie_rp[PCH_RP(7)]" = "{
227 .flags = PCIE_RP_LTR | PCIE_RP_AER,
230 register
"customized_leds" = "0x0843"
231 register
"wake" = "GPE0_DW0_07" #GPP_A7
232 register
"device_index" = "0"
233 device pci
00.0 on
end
235 end #PCIE7 RTL8111K Ethernet NIC
236 device ref pcie_rp8 off
end
237 device ref pch_espi on
238 chip ec
/google
/chromeec
239 use conn0
as mux_conn
[0]
240 use conn1
as mux_conn
[1]
241 device pnp
0c09.0 on
end
244 device ref pmc hidden
245 chip drivers
/intel
/pmc_mux
247 chip drivers
/intel
/pmc_mux
/conn
248 use usb2_port1
as usb2_port
249 use tcss_usb3_port1
as usb3_port
250 device generic
0 alias conn0 on
end
252 chip drivers
/intel
/pmc_mux
/conn
253 use usb2_port2
as usb2_port
254 use tcss_usb3_port2
as usb3_port
255 device generic
1 alias conn1 on
end
261 chip drivers
/generic
/alc1015
262 register
"hid" = ""RTL1015
""
263 device generic
0 on
end
264 end # RT1015 Amplifier