src/mainboard/google/brya/variants/pujjo/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7 #include <fw_config.h>
   8
   9 /* Pad configuration in ramstage for Pujjo */
  10 static const struct pad_config override_gpio_table[] = {
  11         /* A8  : WWAN_RF_DISABLE_ODL */
  12         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  13         /* D3  : WCAM_RST_L ==> NC */
  14         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  15         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  16         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  17         /* D15  : EN_PP2800_WCAM_X ==> NC */
  18         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  19         /* D16  : EN_PP1800_PP1200_WCAM_X ==> NC */
  20         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  21         /* D17 : NC ==> SD_WAKE_N */
  22         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  23         /* F12 : WWAN_RST_L */
  24         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  25         /* H19 : SOC_I2C_SUB_INT_ODL */
  26         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  27         /* H22  : WCAM_MCLK_R ==> NC */
  28         PAD_NC(GPP_H22, NONE),
  29         /* H23 : WWAN_SAR_DETECT_ODL ==> NC */
  30         PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
  31 };
  32
  33 /* Pad configuration in ramstage for Pujjoteen5 */
  34 static const struct pad_config override_5g_gpio_table[] = {
  35         /* A8  : WWAN_RF_DISABLE_ODL */
  36         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  37         /* A12 : WWAN_PCIE_WAKE_ODL */
  38         PAD_CFG_GPI_LOCK(GPP_A12, NONE, LOCK_CONFIG),
  39         /* D3  : WCAM_RST_L ==> NC */
  40         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  41         /* D5  : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */
  42         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
  43         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  44         PAD_CFG_GPO_LOCK(GPP_D6, 1, LOCK_CONFIG),
  45         /* D15  : EN_PP2800_WCAM_X ==> NC */
  46         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  47         /* D16  : EN_PP1800_PP1200_WCAM_X ==> NC */
  48         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  49         /* D17 : NC ==> SD_WAKE_N */
  50         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  51         /* F12 : WWAN_RST_L */
  52         PAD_CFG_GPO(GPP_F12, 0, DEEP),
  53         /* H19 : SOC_I2C_SUB_INT_ODL */
  54         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  55         /* H21  : WCAM_MCLK_R ==> WWAN_PERST_L */
  56         PAD_CFG_GPO(GPP_H21, 0, DEEP),
  57         /* H22  : WCAM_MCLK_R ==> NC */
  58         PAD_NC(GPP_H22, NONE),
  59         /* H23 : WWAN_SAR_DETECT_ODL ==> NC */
  60         PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
  61 };
  62
  63 /* Pad configuration in ramstage for Pujjo LTE EM060 */
  64 static const struct pad_config override_em060_gpio_table[] = {
  65         /* A8  : WWAN_RF_DISABLE_ODL */
  66         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  67         /* D3  : WCAM_RST_L ==> NC */
  68         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  69         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  70         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  71         /* D15  : EN_PP2800_WCAM_X ==> NC */
  72         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  73         /* D16  : EN_PP1800_PP1200_WCAM_X ==> NC */
  74         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  75         /* D17 : NC ==> SD_WAKE_N */
  76         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  77         /* F12 : WWAN_RST_L */
  78         PAD_CFG_GPO(GPP_F12, 1, DEEP),
  79         /* H19 : SOC_I2C_SUB_INT_ODL */
  80         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  81         /* H22  : WCAM_MCLK_R ==> NC */
  82         PAD_NC(GPP_H22, NONE),
  83         /* H23 : WWAN_SAR_DETECT_ODL ==> NC */
  84         PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
  85 };
  86
  87 /* Early pad configuration in bootblock */
  88 static const struct pad_config early_gpio_table[] = {
  89         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
  90         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  91         /*
  92         * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
  93         * requirement. WWAN_EN must be asserted before WWAN_RST_L is released
  94         * (with min delay 0 ms), so this works as long as the pin used for
  95         * WWAN_EN comes before the pin used for WWAN_RST_L.
  96         */
  97         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  98         PAD_CFG_GPO(GPP_D6, 0, DEEP),
  99         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 100         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 101         /* F12 : WWAN_RST_L */
 102         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 103         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 104         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 105         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 106         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 107         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 108         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 109         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 110         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 111         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 112         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 113         /* H12 : UART0_RTS# ==> SD_PERST_L */
 114         PAD_CFG_GPO(GPP_H12, 0, DEEP),
 115         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
 116         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 117 };
 118
 119
 120 /* Early pad configuration in bootblock for Pujjoteen5 */
 121 static const struct pad_config early_5g_gpio_table[] = {
 122         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 123         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 124         /*
 125         * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
 126         * requirement. WWAN_EN must be asserted before WWAN_RST_L is released
 127         * (with min delay 0 ms), so this works as long as the pin used for
 128         * WWAN_EN comes before the pin used for WWAN_RST_L.
 129         */
 130         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
 131         PAD_CFG_GPO(GPP_D6, 0, DEEP),
 132         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 133         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 134         /* F12 : WWAN_RST_L */
 135         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 136         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 137         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 138         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 139         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 140         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 141         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 142         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 143         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 144         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 145         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 146         /* H12 : UART0_RTS# ==> SD_PERST_L */
 147         PAD_CFG_GPO(GPP_H12, 0, DEEP),
 148         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
 149         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 150         /* H21  : WCAM_MCLK_R ==> WWAN_PERST_L */
 151         PAD_CFG_GPO(GPP_H21, 0, DEEP),
 152 };
 153
 154 /* Pad configuration in romstage for Pujjo */
 155 static const struct pad_config romstage_gpio_table[] = {
 156         /* Enable touchscreen, hold in reset */
 157         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 158         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 159         /* C1  : SMBDATA ==> USI_RST_L */
 160         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 161
 162         /* H12 : UART0_RTS# ==> SD_PERST_L */
 163         PAD_CFG_GPO(GPP_H12, 1, DEEP),
 164 };
 165
 166 /* Pad configuration in romstage for Pujjo WWAN EM060 */
 167 static const struct pad_config romstage_em060_gpio_table[] = {
 168         /* H12 : UART0_RTS# ==> SD_PERST_L */
 169         PAD_CFG_GPO(GPP_H12, 1, DEEP),
 170         /* F12 : WWAN_RST_L */
 171         PAD_CFG_GPO(GPP_F12, 1, DEEP),
 172 };
 173
 174 const struct pad_config *variant_gpio_override_table(size_t *num)
 175 {
 176         if (fw_config_probe(FW_CONFIG(WWAN_5G, WWAN_5G_PRESENT))) {
 177                 *num = ARRAY_SIZE(override_5g_gpio_table);
 178                 return override_5g_gpio_table;
 179         } else if (fw_config_probe(FW_CONFIG(LTE_EM060, LTE_EM060_PRESENT))) {
 180                 *num = ARRAY_SIZE(override_em060_gpio_table);
 181                 return override_em060_gpio_table;
 182         } else {
 183                 *num = ARRAY_SIZE(override_gpio_table);
 184                 return override_gpio_table;
 185         }
 186 }
 187
 188 const struct pad_config *variant_early_gpio_table(size_t *num)
 189 {
 190         if (fw_config_probe(FW_CONFIG(WWAN_5G, WWAN_5G_PRESENT))) {
 191                 *num = ARRAY_SIZE(early_5g_gpio_table);
 192                 return early_5g_gpio_table;
 193         } else {
 194                 *num = ARRAY_SIZE(early_gpio_table);
 195                 return early_gpio_table;
 196         }
 197 }
 198
 199 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 200 {
 201         if (fw_config_probe(FW_CONFIG(LTE_EM060, LTE_EM060_PRESENT))) {
 202                 *num = ARRAY_SIZE(romstage_em060_gpio_table);
 203                 return romstage_em060_gpio_table;
 204         } else {
 205                 *num = ARRAY_SIZE(romstage_gpio_table);
 206                 return romstage_gpio_table;
 207         }
 208 }