src/mainboard/google/brya/variants/redrix/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A17 : DISP_MISCC ==> NC */
  11         PAD_NC(GPP_A17, NONE),
  12         /* A19 : DDSP_HPD1 ==> NC */
  13         PAD_NC(GPP_A19, NONE),
  14         /* A20 : DDSP_HPD2 ==> NC */
  15         PAD_NC(GPP_A20, NONE),
  16         /* A21 : DDPC_CTRCLK ==> NC */
  17         PAD_NC(GPP_A21, NONE),
  18         /* A22 : DDPC_CTRLDATA ==> NC */
  19         PAD_NC(GPP_A22, NONE),
  20
  21         /* B3  : PROC_GP2 ==> NC */
  22         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  23         /* B15  : TIME_SYNC0 ==> NC */
  24         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  25
  26         /* C3 : SML0CLK ==> NC */
  27         PAD_NC(GPP_C3, NONE),
  28         /* C4 : SML0DATA ==> NC */
  29         PAD_NC(GPP_C4, NONE),
  30
  31         /* D7  : SRCCLKREQ2# ==> NC */
  32         PAD_NC(GPP_D7, NONE),
  33         /* D13 : ISH_UART0_RXD ==> NC */
  34         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  35
  36         /* D16 : ISH_UART0_CTS# ==> EN_NVM_SENSOR_PWR */
  37         PAD_CFG_GPO(GPP_D16, 1, DEEP),
  38
  39         /* E3  : PROC_GP0 ==> NC */
  40         PAD_NC(GPP_E3, NONE),
  41         /* E7  : PROC_GP1 ==> NC */
  42         PAD_NC(GPP_E7, NONE),
  43         /* E16 : RSVD_TP ==> WWAN_RST_L */
  44         PAD_CFG_GPO(GPP_E16, 1, DEEP),
  45         /* E20 : DDP2_CTRLCLK ==> NC */
  46         PAD_NC(GPP_E20, NONE),
  47         /* E22 : DDPA_CTRLCLK ==> NC */
  48         PAD_NC(GPP_E22, NONE),
  49         /* E23 : DDPA_CTRLDATA ==> NC */
  50         PAD_NC(GPP_E23, NONE),
  51         /* F20 : EXT_PWR_GATE# ==> NC */
  52         PAD_NC(GPP_F20, NONE),
  53
  54         /* H3  : SX_EXIT_HOLDOFF# ==> NC */
  55         PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
  56         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  57         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
  58         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  59         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
  60         /* H20 : IMGCLKOUT1 ==> NC */
  61         PAD_NC(GPP_H20, NONE),
  62         /* H21 : IMGCLKOUT2 ==> Privacy screen */
  63         PAD_CFG_GPO(GPP_H21, 0, DEEP),
  64
  65         /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
  66         PAD_NC(GPP_R6, NONE),
  67         /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
  68         PAD_NC(GPP_R7, NONE),
  69
  70         /* S4 : SNDW2_CLK ==> NC */
  71         PAD_NC(GPP_S4, NONE),
  72         /* S5 : SNDW2_DATA ==> NC */
  73         PAD_NC(GPP_S5, NONE),
  74         /* S6 : SNDW3_CLK ==> NC */
  75         PAD_NC(GPP_S6, NONE),
  76         /* S7 : SNDW3_DATA ==> NC */
  77         PAD_NC(GPP_S7, NONE),
  78         /*
  79          * E0 : SATAXPCIE0 ==> WWAN_PERST_L
  80          * Drive high here, so that PERST_L is sequenced after RST_L
  81          */
  82         PAD_CFG_GPO(GPP_E0, 1, DEEP),
  83 };
  84
  85 /* Early pad configuration in bootblock */
  86 static const struct pad_config early_gpio_table[] = {
  87         /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
  88         PAD_CFG_GPO(GPP_A12, 1, DEEP),
  89         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  90         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  91         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  92         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
  93         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  94         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
  95         /*
  96          * D1  : ISH_GP1 ==> FP_RST_ODL
  97          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
  98          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
  99          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 100          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 101          * FPMCU not working after a S3 resume. This is a known issue.
 102          */
 103         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 104         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 105         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 106         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 107         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 108         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
 109         PAD_CFG_GPO(GPP_E0, 0, DEEP),
 110         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 111         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 112         /* E15 : RSVD_TP ==> PCH_WP_OD */
 113         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 114         /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
 115         PAD_CFG_GPO(GPP_E16, 0, DEEP),
 116         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 117         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 118         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
 119         PAD_CFG_GPO(GPP_F21, 0, DEEP),
 120         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 121         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 122         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 123         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 124         /*
 125          * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
 126          * then deassert PERST# in romstage
 127          */
 128         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 129         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 130         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 131         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 132 };
 133
 134 static const struct pad_config romstage_gpio_table[] = {
 135         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 136         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 137
 138         /* Enable touchscreen, hold in reset */
 139         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 140         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 141         /* C1  : SMBDATA ==> USI_RST_L */
 142         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 143
 144         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 145         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 146         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 147         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 148
 149         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 150         PAD_CFG_GPO(GPP_F21, 1, DEEP),
 151 };
 152
 153 const struct pad_config *variant_gpio_override_table(size_t *num)
 154 {
 155         *num = ARRAY_SIZE(override_gpio_table);
 156         return override_gpio_table;
 157 }
 158
 159 const struct pad_config *variant_early_gpio_table(size_t *num)
 160 {
 161         *num = ARRAY_SIZE(early_gpio_table);
 162         return early_gpio_table;
 163 }
 164
 165 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 166 {
 167         *num = ARRAY_SIZE(romstage_gpio_table);
 168         return romstage_gpio_table;
 169 }