src/mainboard/google/brya/variants/taeko4es/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A6  : ESPI_ALERT1# ==> NC */
  11         PAD_NC(GPP_A6, NONE),
  12         /* A7  : SRCCLK_OE7# ==> NC */
  13         PAD_NC(GPP_A7, NONE),
  14         /* A8  : SRCCLKREQ7# ==> NC */
  15         PAD_NC(GPP_A8, NONE),
  16         /* A12 : SATAXPCIE1 ==> NC */
  17         PAD_NC(GPP_A12, NONE),
  18         /* A14 : USB_OC1# ==> NC */
  19         PAD_NC(GPP_A14, NONE),
  20         /* A15 : USB_OC2# ==> NC */
  21         PAD_NC(GPP_A15, NONE),
  22         /* A18 : DDSP_HPDB ==> NC */
  23         PAD_NC(GPP_A18, NONE),
  24         /* A19 : DDSP_HPD1 ==> NC */
  25         PAD_NC(GPP_A19, NONE),
  26         /* A20 : DDSP_HPD2 ==> NC */
  27         PAD_NC(GPP_A20, NONE),
  28         /* A21 : DDPC_CTRCLK ==> NC */
  29         PAD_NC(GPP_A21, NONE),
  30         /* A22 : DDPC_CTRLDATA ==> NC */
  31         PAD_NC(GPP_A22, NONE),
  32
  33         /* B2  : VRALERT# ==> NC */
  34         PAD_NC(GPP_B2, NONE),
  35         /* B3  : PROC_GP2 ==> NC */
  36         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  37         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  38         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  39         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  40         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  41         /* B15 : TIME_SYNC0 ==> NC */
  42         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  43
  44         /* C3 : SML0CLK ==> NC */
  45         PAD_NC(GPP_C3, NONE),
  46         /* C4 : SML0DATA ==> NC */
  47         PAD_NC(GPP_C4, NONE),
  48         /* C6  : SML1CLK ==> NC */
  49         PAD_NC(GPP_C6, NONE),
  50
  51         /* D3  : ISH_GP3 ==> NC */
  52         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  53         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
  54         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
  55         /* D9  : ISH_SPI_CS# ==> NC */
  56         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  57         /* D10 : ISH_SPI_CLK ==> NC */
  58         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  59         /* D13 : ISH_UART0_RXD ==> NC */
  60         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  61         /* D14 : ISH_UART0_TXD ==> NC */
  62         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
  63         /* D15 : ISH_UART0_RTS# ==> NC */
  64         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  65         /* D16 : ISH_UART0_CTS# ==> NC */
  66         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  67         /* D17 : UART1_RXD ==> NC */
  68         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  69
  70         /* E0  : SATAXPCIE0 ==> NC */
  71         PAD_NC(GPP_E0, NONE),
  72         /* E4  : SATA_DEVSLP0 ==> NC */
  73         PAD_NC(GPP_E4, NONE),
  74         /* E5  : SATA_DEVSLP1 ==> NC */
  75         PAD_NC(GPP_E5, NONE),
  76         /* E10 : THC0_SPI1_CS# ==> NC */
  77         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
  78         /* E16 : RSVD_TP ==> NC */
  79         PAD_NC(GPP_E16, NONE),
  80         /* E17 : THC0_SPI1_INT# ==> NC */
  81         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  82         /* E18 : DDP1_CTRLCLK ==> NC */
  83         PAD_NC(GPP_E18, NONE),
  84         /* E19 : DDP1_CTRLDATA ==> NC */
  85         PAD_NC(GPP_E19, NONE),
  86         /* E20 : DDP2_CTRLCLK ==> NC */
  87         PAD_NC(GPP_E20, NONE),
  88         /* E21 : DDP2_CTRLDATA ==> NC */
  89         PAD_NC(GPP_E21, NONE),
  90
  91         /* F6  : CNV_PA_BLANKING ==> NC */
  92         PAD_NC(GPP_F6, NONE),
  93         /* F19 : SRCCLKREQ6# ==> NC */
  94         PAD_NC(GPP_F19, NONE),
  95         /* F20 : EXT_PWR_GATE# ==> NC */
  96         PAD_NC(GPP_F20, NONE),
  97         /* F21 : EXT_PWR_GATE2# ==> NC */
  98         PAD_NC(GPP_F21, NONE),
  99         /* F22 : VNN_CTRL ==> VNN_CTRL */
 100         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 101         /* F23 : BP105_CTRL ==> PP1050_CTRL */
 102         PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 103
 104         /* H8  : I2C4_SDA ==> NC */
 105         PAD_NC(GPP_H8, NONE),
 106         /* H9  : I2C4_SCL ==> NC */
 107         PAD_NC(GPP_H9, NONE),
 108         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 109         PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
 110         /* H15 : DDPB_CTRLCLK ==> NC */
 111         PAD_NC(GPP_H15, NONE),
 112         /* H17 : DDPB_CTRLDATA ==> NC */
 113         PAD_NC(GPP_H17, NONE),
 114         /* H19 : SRCCLKREQ4# ==> NC */
 115         PAD_NC(GPP_H19, NONE),
 116         /* H21 : IMGCLKOUT2 ==>  NC */
 117         PAD_NC(GPP_H21, NONE),
 118         /* H22 : IMGCLKOUT3 ==> NC */
 119         PAD_NC(GPP_H22, NONE),
 120         /* H23 : SRCCLKREQ5# ==> NC */
 121         PAD_NC(GPP_H23, NONE),
 122
 123         /* R7 : I2S2_RXD ==> NC */
 124         PAD_NC(GPP_R7, NONE),
 125
 126         /* S0 : SNDW0_CLK ==> NC */
 127         PAD_NC(GPP_S0, NONE),
 128         /* S1 : SNDW0_DATA ==> NC */
 129         PAD_NC(GPP_S1, NONE),
 130         /* S4 : SNDW2_CLK ==> NC */
 131         PAD_NC(GPP_S4, NONE),
 132         /* S5 : SNDW2_DATA ==> NC */
 133         PAD_NC(GPP_S5, NONE),
 134         /* S6 : SNDW3_CLK ==> NC */
 135         PAD_NC(GPP_S6, NONE),
 136         /* S7 : SNDW3_DATA ==> NC */
 137         PAD_NC(GPP_S7, NONE),
 138
 139         /* GPD11: LANPHYC ==> WWAN_CONFIG1 */
 140         PAD_NC(GPD11, NONE),
 141 };
 142
 143 /* Early pad configuration in bootblock */
 144 static const struct pad_config early_gpio_table[] = {
 145         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 146         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 147         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 148         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 149         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
 150         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 151         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
 152         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 153         /*
 154          * D1  : ISH_GP1 ==> FP_RST_ODL
 155          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 156          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 157          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 158          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 159          * FPMCU not working after a S3 resume. This is a known issue.
 160          */
 161         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 162         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 163         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 164         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 165         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 166         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 167         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 168         /* E15 : RSVD_TP ==> PCH_WP_OD */
 169         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 170         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 171         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 172         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 173         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 174         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 175         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 176         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 177         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 178         /* CPU PCIe VGPIO for PEG60 */
 179         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 180         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 181         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 182         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 183         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 184         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 185         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 186         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 187         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 188         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 189         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 190         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 191         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 192         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 193         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 194         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 195         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 196         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 197         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 198         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 199 };
 200
 201 static const struct pad_config romstage_gpio_table[] = {
 202         /*
 203          * B4  : PROC_GP3 ==> SSD_PERST_L
 204          * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 205          */
 206         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 207
 208         /* Enable touchscreen, hold in reset */
 209         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 210         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 211         /* C1  : SMBDATA ==> USI_RST_L */
 212         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 213
 214         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 215         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 216         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 217         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 218 };
 219
 220 const struct pad_config *variant_gpio_override_table(size_t *num)
 221 {
 222         *num = ARRAY_SIZE(override_gpio_table);
 223         return override_gpio_table;
 224 }
 225
 226 const struct pad_config *variant_early_gpio_table(size_t *num)
 227 {
 228         *num = ARRAY_SIZE(early_gpio_table);
 229         return early_gpio_table;
 230 }
 231
 232 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 233 {
 234         *num = ARRAY_SIZE(romstage_gpio_table);
 235         return romstage_gpio_table;
 236 }