src/mainboard/google/brya/variants/vell/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6 #include <soc/romstage.h>
   7
   8 static const struct mb_cfg baseboard_memcfg = {
   9         .type = MEM_TYPE_LP5X,
  10
  11         /* Leave Rcomp unspecified to use the FSP optimized defaults */
  12
  13         /* DQ byte map */
  14         .lpx_dq_map = {
  15                 .ddr0 = {
  16                         .dq0 = {  4,  0,  1,  3,  7,  5,  6,  2, },
  17                         .dq1 = {  9, 13, 12,  8, 15, 10, 14, 11, },
  18                 },
  19                 .ddr1 = {
  20                         .dq1 = {  0,  2,  1,  3,  7,  5,  6,  4, },
  21                         .dq0 = { 10,  8, 11,  9, 13, 15, 14, 12, },
  22                 },
  23                 .ddr2 = {
  24                         .dq0 = {  3,  7,  2,  6,  4,  1,  5,  0, },
  25                         .dq1 = { 12, 14, 15, 13, 11,  8, 10,  9, },
  26                 },
  27                 .ddr3 = {
  28                         .dq1 = {  7,  6,  4,  5,  0,  3,  1,  2, },
  29                         .dq0 = {  9, 13,  8, 12, 15, 10, 14, 11, },
  30                 },
  31                 .ddr4 = {
  32                         .dq1 = {  7,  5,  4,  6,  2,  0,  1,  3, },
  33                         .dq0 = { 15, 14, 12, 13, 10,  9,  8, 11, },
  34                 },
  35                 .ddr5 = {
  36                         .dq1 = {  3,  7,  2,  6,  0,  4,  5,  1, },
  37                         .dq0 = {  9, 10, 11,  8, 12, 15, 13, 14, },
  38                 },
  39                 .ddr6 = {
  40                         .dq1 = {  1,  0,  3,  2,  7,  5,  4,  6, },
  41                         .dq0 = { 11,  8, 10,  9, 12, 14, 13, 15, },
  42                 },
  43                 .ddr7 = {
  44                         .dq0 = {  3,  2,  1,  0,  7,  5,  6,  4, },
  45                         .dq1 = {  8,  9, 10, 12, 14, 11, 13, 15, },
  46                 },
  47         },
  48
  49         /* DQS CPU<>DRAM map */
  50         .lpx_dqs_map = {
  51                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
  52                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
  53                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  54                 .ddr3 = { .dqs0 = 1, .dqs1 = 0 },
  55                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
  56                 .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
  57                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  58                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  59         },
  60
  61         .LpDdrDqDqsReTraining = 1,
  62
  63         .ect = true, /* Early Command Training */
  64         .UserBd =  BOARD_TYPE_ULT_ULX_T4,
  65
  66         .lp5x_config = {
  67                 .ccc_config = 0xff,
  68         },
  69 };
  70
  71 const struct mb_cfg *variant_memory_params(void)
  72 {
  73         return &baseboard_memcfg;
  74 }
  75
  76 int variant_memory_sku(void)
  77 {
  78         /*
  79          * Memory configuration board straps
  80          * GPIO_MEM_CONFIG_0    GPP_E3
  81          * GPIO_MEM_CONFIG_1    GPP_E2
  82          * GPIO_MEM_CONFIG_2    GPP_E1
  83          * GPIO_MEM_CONFIG_3    GPP_E7
  84          */
  85         gpio_t spd_gpios[] = {
  86                 GPP_E3,
  87                 GPP_E2,
  88                 GPP_E1,
  89                 GPP_E7,
  90         };
  91
  92         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  93 }
  94
  95 bool variant_is_half_populated(void)
  96 {
  97         /* GPIO_MEM_CH_SEL GPP_E5 */
  98         return gpio_get(GPP_E5);
  99 }