src/mainboard/google/parrot/devicetree.cb

   1 chip northbridge/intel/sandybridge
   2         # IGD Displays
   3         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
   4
   5         # Enable DisplayPort B Hotplug with 6ms pulse
   6         register "gpu_dp_b_hotplug" = "0x06"
   7
   8         # Enable Panel as LVDS and configure power delays
   9         register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
  10         register "gpu_panel_power_cycle_delay" = "5"            # 400ms
  11         register "gpu_panel_power_up_delay" = "500"             # 50ms
  12         register "gpu_panel_power_down_delay" = "150"           # 15ms
  13         register "gpu_panel_power_backlight_on_delay" = "2100"  # 210ms
  14         register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
  15
  16         # Set backlight PWM values
  17         register "gpu_cpu_backlight" = "0x000001d4"
  18         register "gpu_pch_backlight" = "0x03aa0000"
  19
  20         register "spd_addresses" = "{0x50, 0, 0x52, 0}"
  21         register "ec_present" = "1"
  22         # FIXME: Native raminit requires reduced max clock
  23         register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
  24
  25         register "usb_port_config" = "{
  26                 { 0, 3, 0x0000 },
  27                 { 1, 0, 0x0040 },
  28                 { 1, 1, 0x0040 },
  29                 { 1, 1, 0x0040 },
  30                 { 0, 3, 0x0000 },
  31                 { 0, 3, 0x0000 },
  32                 { 0, 3, 0x0000 },
  33                 { 0, 3, 0x0000 },
  34                 { 1, 4, 0x0040 },
  35                 { 0, 4, 0x0000 },
  36                 { 1, 4, 0x0040 },
  37                 { 0, 4, 0x0000 },
  38                 { 0, 4, 0x0000 },
  39                 { 0, 4, 0x0000 },}"
  40
  41         device domain 0 on
  42                 device ref host_bridge on end # host bridge
  43                 device ref igd on end # vga controller
  44
  45                 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
  46                         # GPI routing
  47                         #  0 No effect (default)
  48                         #  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  49                         #  2 SCI (if corresponding GPIO_EN bit is also set)
  50                         # Set Lid Switch to SMI to capture in recovery mode.  It gets reset to
  51                         # SCI mode when we go to ACPI mode.
  52                         register "alt_gp_smi_en" = "0x8100"
  53                         register "gpi7_routing" = "2"
  54                         register "gpi8_routing" = "1"
  55                         register "gpi15_routing" = "1" #lid switch gpe
  56
  57                         register "sata_port_map" = "0x1"
  58
  59                         # EC range is 0xFD60 (EC_IO) and 0x68/0x6C
  60                         register "gen1_dec" = "0x0004fd61"
  61                         register "gen2_dec" = "0x00040069"
  62
  63                         # Enable zero-based linear PCIe root port functions
  64                         register "pcie_port_coalesce" = "true"
  65
  66                         device ref mei1 on end # Management Engine Interface 1
  67                         device ref mei2 off end # Management Engine Interface 2
  68                         device ref me_ide_r off end # Management Engine IDE-R
  69                         device ref me_kt off end # Management Engine KT
  70                         device ref gbe off end # Intel Gigabit Ethernet
  71                         device ref ehci2 on end # USB2 EHCI #2
  72                         device ref hda on end # High Definition Audio
  73                         device ref pcie_rp1 off end # PCIe Port #1
  74                         device ref pcie_rp2 on end # PCIe Port #2 (WLAN)
  75                         device ref pcie_rp3 on end # PCIe Port #3 (ETH0)
  76                         device ref pcie_rp4 off end # PCIe Port #4
  77                         device ref pcie_rp5 off end # PCIe Port #5
  78                         device ref pcie_rp6 off end # PCIe Port #6
  79                         device ref pcie_rp7 off end # PCIe Port #7
  80                         device ref pcie_rp8 off end # PCIe Port #8
  81                         device ref ehci1 on end # USB2 EHCI #1
  82                         device ref pci_bridge off end # PCI bridge
  83                         device ref lpc on
  84                                 chip ec/compal/ene932
  85                                         # 60/64 KBC
  86                                         device pnp ff.1 on # dummy address
  87                                         end
  88                                 end
  89                         end # LPC bridge
  90                         device ref sata1 on end # SATA Controller 1
  91                         device ref smbus on
  92                                 subsystemid 0x04B4 0x18D1
  93                         end # SMBus
  94                         device ref sata2 off end # SATA Controller 2
  95                         device ref thermal on end # Thermal
  96                 end
  97         end
  98 end