src/mainboard/intel/saddlebrook/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef MAINBOARD_GPIO_H
   4 #define MAINBOARD_GPIO_H
   5
   6 #include <soc/gpe.h>
   7 #include <soc/gpio.h>
   8
   9 /* EC in RW */
  10 #define GPIO_EC_IN_RW           GPP_C6
  11
  12 /* BIOS Flash Write Protect */
  13 #define GPIO_PCH_WP             GPP_C23
  14
  15 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
  16 #define GPE_EC_WAKE             GPE0_LAN_WAK
  17
  18 /* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
  19 #define GPE_WLAN_WAKE           GPE0_DW0_16
  20
  21 /* Input device interrupt configuration */
  22 #define TOUCHPAD_INT_L          GPP_B3_IRQ
  23 #define TOUCHSCREEN_INT_L       GPP_E7_IRQ
  24 #define MIC_INT_L               GPP_F10_IRQ
  25
  26 /* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
  27 #define EC_SCI_GPI              GPE0_DW2_16
  28 #define EC_SMI_GPI              GPP_E15
  29
  30 #ifndef __ACPI__
  31 /* Pad configuration in ramstage. */
  32 static const struct pad_config gpio_table[] = {
  33 /* EC_PCH_RCIN */       PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  34 /* LPC_LAD_0 */         PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
  35 /* LPC_LAD_1 */         PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
  36 /* LPC_LAD_2 */         PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
  37 /* LPC_LAD_3 */         PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
  38 /* LPC_FRAME */         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  39 /* LPC_SERIRQ */        PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  40 /* PIRQA# */            PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
  41 /* LPC_CLKRUN */        PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  42 /* EC_LPC_CLK */        PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
  43 /* PCH_LPC_CLK */       PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
  44 /* EC_HID_INT */        PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
  45 /* ISH_KB_PROX_INT */   PAD_CFG_GPI(GPP_A12, NONE, DEEP),
  46 /* PCH_SUSPWRACB */     PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  47 /* PM_SUS_STAT */       PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  48 /* PCH_SUSACK */        PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  49 /* SD_1P8_SEL */
  50 /* SD_PWR_EN */
  51 /* ACCEL INTERRUPT */   PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  52 /* ISH_GP1 */           /* GPP_A19 */
  53 /* GYRO_DRDY */
  54 /* FLIP_ACCEL_INT */
  55 /* GYRO_INT */
  56 /* ISH_GP5 */           /* GPP_A23 */
  57
  58 /* CORE_VID0 */         /* GPP_B0 */
  59 /* CORE_VID1 */         /* GPP_B1 */
  60 /* HSJ_MIC_DET */
  61 /* TRACKPAD_INT */                      PAD_CFG_GPO(GPP_B3, 1, DEEP),
  62 /* BT_RF_KILL */        PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
  63 /* SRCCLKREQ0# */       /* GPP_B5 */
  64 /* WIFI_CLK_REQ */
  65 /* KEPLR_CLK_REQ */     PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  66 /* SRCCLKREQ3# */       /* GPP_B8 */
  67 /* SSD_CLK_REQ */
  68 /* SRCCLKREQ5# */       /* GPP_B10 */
  69 /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  70 /* PM_SLP_S0 */         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  71 /* PCH_PLT_RST */       PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  72 /* GPP_B_14_SPKR */     PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1),
  73 /* GSPI0_CS# */         /* GPP_B15 */
  74 /* WLAN_PCIE_WAKE */
  75 /* SSD_PCIE_WAKE */     PAD_CFG_GPO(GPP_B17, 1, DEEP),
  76 /* GSPI0_MOSI */        /* GPP_B18 */
  77 /* CCODEC_SPI_CS */
  78 /* CODEC_SPI_CLK */
  79 /* CODEC_SPI_MISO */
  80 /* CODEC_SPI_MOSI */
  81 /* SM1ALERT# */         PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF1),
  82
  83 /* SMB_CLK */           PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  84 /* SMB_DATA */          PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
  85 /* SMBALERT# */         PAD_CFG_NF(GPP_C2, DN_20K, DEEP, NF1),
  86 /* M2_WWAN_PWREN */     PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
  87 /* SML0DATA */          PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
  88 /* SML0ALERT# */        /* GPP_C5 */
  89 /* EC_IN_RW */          PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
  90 /* USB_CTL */           PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
  91 /* UART0_RXD */         /* GPP_C8 */
  92 /* UART0_TXD */         /* GPP_C9 */
  93 /* NFC_RST* */
  94 /* EN_PP3300_KEPLER */
  95 /* PCH_MEM_CFG0 */
  96 /* PCH_MEM_CFG1 */
  97 /* PCH_MEM_CFG2 */
  98 /* PCH_MEM_CFG3 */
  99 /* I2C0_SDA */
 100 /* I2C0_SCL */
 101 /* I2C1_SDA */
 102 /* I2C1_SCL */
 103 /* GD_UART2_RXD */
 104 /* GD_UART2_TXD */
 105 /* TCH_PNL_PWREN */
 106 /* SPI_WP_STATUS */
 107
 108 /* ITCH_SPI_CS */       /* GPP_D0 */
 109 /* ITCH_SPI_CLK */      /* GPP_D1 */
 110 /* ITCH_SPI_MISO_1 */   /* GPP_D2 */
 111 /* ITCH_SPI_MISO_0 */   /* GPP_D3 */
 112 /* CAM_FLASH_STROBE */
 113 /* EN_PP3300_DX_EMMC */
 114 /* EN_PP1800_DX_EMMC */
 115 /* SH_I2C1_SDA */
 116 /* SH_I2C1_SCL */
 117 /* TBD */
 118 /* USB_A0_ILIM_SEL */
 119 /* USB_A1_ILIM_SEL */
 120 /* EN_PP3300_DX_CAM */
 121 /* EN_PP1800_DX_AUDIO */
 122 /* ISH_UART0_TXD */     /* GPP_D14 */
 123 /* ISH_UART0_RTS */     /* GPP_D15 */
 124 /* ISH_UART0_CTS */     /* GPP_D16 */
 125 /* DMIC_CLK_1 */
 126 /* DMIC_DATA_1 */
 127 /* DMIC_CLK_0 */
 128 /* DMIC_DATA_0 */
 129 /* ITCH_SPI_D2 */       /* GPP_D21 */
 130 /* ITCH_SPI_D3 */       /* GPP_D22 */
 131 /* I2S_MCLK */
 132
 133 /* SPI_TPM_IRQ */       PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
 134 /* SATAXPCIE1 */        /* GPP_E1 */
 135 /* SSD_PEDET */
 136 /* CPU_GP0 */
 137 /* SSD_SATA_DEVSLP */   PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
 138 /* SATA_DEVSLP1 */      /* GPP_E5 */
 139 /* SATA_DEVSLP2 */      /* GPP_E6 */
 140 /* TCH_PNL_INTR* */
 141 /* SATALED# */          PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 142 /* USB2_OC_0 */         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 143 /* USB2_OC_1 */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 144 /* USB2_OC_2 */         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 145 /* USB2_OC_3 */         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 146
 147 /* I2S2_SCLK */
 148 /* I2S2_SFRM */
 149 /* I2S2_TXD */          PAD_CFG_GPO(GPP_F2, 0, DEEP),
 150 /* I2S2_RXD */
 151 /* I2C2_SDA */          /* GPP_F4 */
 152 /* I2C2_SCL */          /* GPP_F5 */
 153 /* I2C3_SDA */          /* GPP_F6 */
 154 /* I2C3_SCL */          /* GPP_F7 */
 155 /* I2C4_SDA */
 156 /* I2C4_SDA */
 157 /* AUDIO_IRQ */
 158 /* I2C5_SCL */          /* GPP_F11 */
 159 /* EMMC_CMD */          PAD_CFG_GPI(GPP_F12, NONE, DEEP),
 160 /* EMMC_DATA0 */        PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 161 /* EMMC_DATA1 */        PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 162 /* EMMC_DATA2 */        PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 163 /* EMMC_DATA3 */        PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 164 /* EMMC_DATA4 */        PAD_CFG_GPO(GPP_F17, 1, DEEP),
 165 /* EMMC_DATA5 */        PAD_CFG_GPO(GPP_F18, 1, DEEP),
 166 /* EMMC_DATA6 */        PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 167 /* EMMC_DATA7 */        PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 168 /* EMMC_RCLK */         PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 169 /* EMMC_CLK */          PAD_CFG_GPO(GPP_F22, 1, DEEP),
 170                         /* GPP_F23 */
 171
 172 /* SD_CMD */            /* GPP_G0 */
 173 /* SD_DATA0 */
 174 /* SD_DATA1 */
 175 /* SD_DATA2 */
 176 /* SD_DATA3 */
 177 /* SD_CD# */
 178 /* SD_CLK */
 179 /* SD_WP */
 180 /* TBD */       PAD_CFG_GPO(GPP_G8, 1, DEEP),
 181 /* TBD */
 182 /* TBD */
 183 /* TBD */
 184 /* TBD */
 185 /* TBD */
 186 /* TBD */
 187 /* TBD */
 188 /* TBD */
 189 /* TBD */
 190 /* TBD */
 191 /* TBD */
 192 /* TBD */
 193 /* TBD */
 194 /* TBD */
 195 /* TBD */       PAD_CFG_GPI(GPP_G23, NONE, DEEP),
 196
 197 /* SD_CMD */            /* GPP_H0 */
 198 /* SD_DATA0 */
 199 /* SD_DATA1 */
 200 /* SD_DATA2 */
 201 /* SD_DATA3 */
 202 /* SD_CD# */
 203 /* SD_CLK */
 204 /* SD_WP */
 205 /* TBD */
 206 /* TBD */
 207 /* TBD */
 208 /* TBD */
 209 /* TBD */
 210 /* TBD */
 211 /* TBD */
 212 /* TBD */
 213 /* TBD */
 214 /* TBD */
 215 /* TBD */
 216 /* TBD */       PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 217 /* TBD */       PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 218 /* TBD */       PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 219 /* TBD */       PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 220 /* TBD */
 221
 222 /* SD_CMD */            PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
 223 /* SD_CMD */            PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
 224 /* SD_CMD */            PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
 225 /* SD_CMD */            PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
 226 /* SD_CMD */            PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
 227 /* SD_CMD */            PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
 228 /* SD_CMD */            PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
 229 /* SD_CMD */            PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
 230 /* SD_CMD */            PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
 231 /* SD_CMD */            PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
 232 /* SD_CMD */            PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
 233
 234 /* PCH_BATLOW */        PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 235 /* EC_PCH_ACPRESENT */  PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 236 /* EC_PCH_WAKE */       PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 237 /* EC_PCH_PWRBTN */     PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 238 /* PM_SLP_S3# */        PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 239 /* PM_SLP_S4# */        PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 240 /* PM_SLP_SA# */        PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 241                         /* GPD7 */
 242 /* PM_SUSCLK */         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 243 /* PCH_SLP_WLAN# */     PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 244 /* PM_SLP_S5# */        PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
 245 /* LANPHYC */           PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
 246 };
 247
 248 /* Early pad configuration in bootblock */
 249 static const struct pad_config early_gpio_table[] = {
 250 /* UART0_CTS# */        PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
 251 };
 252
 253 #endif
 254
 255 #endif