src/superio/winbond/w83627hf/superio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <device/device.h>
   4 #include <device/pnp.h>
   5 #include <superio/conf_mode.h>
   6 #include <superio/hwm5_conf.h>
   7 #include <console/console.h>
   8 #include <pc80/keyboard.h>
   9 #include <option.h>
  10
  11 #include "w83627hf.h"
  12
  13 static void enable_hwm_smbus(struct device *dev)
  14 {
  15         u8 reg8;
  16
  17         /* Configure pins 91/92 as SDA/SCL (I2C bus). */
  18         reg8 = pnp_read_config(dev, 0x2b);
  19         reg8 &= 0x3f;
  20         pnp_write_config(dev, 0x2b, reg8);
  21 }
  22
  23 static void init_acpi(struct device *dev)
  24 {
  25         u8 value;
  26         unsigned int power_on = get_uint_option("power_on_after_fail", 1);
  27
  28         pnp_enter_conf_mode(dev);
  29         pnp_set_logical_device(dev);
  30         value = pnp_read_config(dev, 0xE4);
  31         value &= ~(3 << 5);
  32         if (power_on)
  33                 value |= (1 << 5);
  34         pnp_write_config(dev, 0xE4, value);
  35         pnp_exit_conf_mode(dev);
  36 }
  37
  38 static void init_hwm(u16 base)
  39 {
  40         u8 reg, value;
  41         int i;
  42
  43         u8 hwm_reg_values[] = {
  44         /*      reg   mask  data */
  45                 0x40, 0xff, 0x81, /* Start HWM. */
  46                 0x48, 0xaa, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
  47                 0x4a, 0x21, 0x21, /* Set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1. */
  48                 0x4e, 0x80, 0x00,
  49                 0x43, 0x00, 0xff,
  50                 0x44, 0x00, 0x3f,
  51                 0x4c, 0xbf, 0x18,
  52                 0x4d, 0xff, 0x80, /* Turn off beep */
  53         };
  54
  55         for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
  56                 reg = hwm_reg_values[i];
  57                 value = pnp_read_hwm5_index(base, reg);
  58                 value &= 0xff & hwm_reg_values[i + 1];
  59                 value |= 0xff & hwm_reg_values[i + 2];
  60                 printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
  61                        "value = 0x%02x\n", base, reg, value);
  62                 pnp_write_hwm5_index(base, reg, value);
  63         }
  64 }
  65
  66 static void w83627hf_init(struct device *dev)
  67 {
  68         struct resource *res0;
  69
  70         if (!dev->enabled)
  71                 return;
  72
  73         switch (dev->path.pnp.device) {
  74         case W83627HF_KBC:
  75                 pc_keyboard_init(NO_AUX_DEVICE);
  76                 break;
  77         case W83627HF_HWM:
  78                 res0 = find_resource(dev, PNP_IDX_IO0);
  79                 init_hwm(res0->base);
  80                 break;
  81         case W83627HF_ACPI:
  82                 init_acpi(dev);
  83                 break;
  84         }
  85 }
  86
  87 static void w83627hf_pnp_enable_resources(struct device *dev)
  88 {
  89         pnp_enable_resources(dev);
  90
  91         pnp_enter_conf_mode(dev);
  92         switch (dev->path.pnp.device) {
  93         case W83627HF_HWM:
  94                 printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n");
  95                 enable_hwm_smbus(dev);
  96                 break;
  97         }
  98         pnp_exit_conf_mode(dev);
  99 }
 100
 101 static struct device_operations ops = {
 102         .read_resources   = pnp_read_resources,
 103         .set_resources    = pnp_set_resources,
 104         .enable_resources = w83627hf_pnp_enable_resources,
 105         .enable           = pnp_alt_enable,
 106         .init             = w83627hf_init,
 107         .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
 108 };
 109
 110 static struct pnp_info pnp_dev_info[] = {
 111         { NULL, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
 112         { NULL, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
 113         { NULL, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
 114         { NULL, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },
 115         { NULL, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
 116                 0x07ff, 0x07ff, },
 117         { NULL, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
 118         { NULL, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
 119                 0x07ff, 0x07fe, },
 120         { NULL, W83627HF_GPIO2, },
 121         { NULL, W83627HF_GPIO3, },
 122         { NULL, W83627HF_ACPI, },
 123         { NULL, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },
 124 };
 125
 126 static void enable_dev(struct device *dev)
 127 {
 128         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 129 }
 130
 131 struct chip_operations superio_winbond_w83627hf_ops = {
 132         .name = "Winbond W83627HF Super I/O",
 133         .enable_dev = enable_dev,
 134 };