src/mainboard/asus/p5gc-mx/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <cf9_reset.h>
   5 #include <console/console.h>
   6 #include <cpu/cpu.h>
   7 #include <cpu/intel/speedstep.h>
   8 #include <cpu/x86/msr.h>
   9 #include <device/pnp_ops.h>
  10 #include <northbridge/intel/i945/i945.h>
  11 #include <southbridge/intel/i82801gx/i82801gx.h>
  12 #include <stdint.h>
  13 #include <superio/winbond/common/winbond.h>
  14 #include <superio/winbond/w83627dhg/w83627dhg.h>
  15
  16
  17 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  18 #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
  19
  20 /*
  21  * BSEL0 is connected with GPIO32
  22  * BSEL1 is connected with GPIO33 with inversed logic
  23  * BSEL2 is connected with GPIO55
  24  */
  25 static int setup_sio_gpio(u8 bsel)
  26 {
  27         int need_reset = 0;
  28         u8 reg, old_reg;
  29
  30         pnp_enter_ext_func_mode(GPIO_DEV);
  31         pnp_set_logical_device(GPIO_DEV);
  32
  33         reg = 0x9a;
  34         old_reg = pnp_read_config(GPIO_DEV, 0x2c);
  35         pnp_write_config(GPIO_DEV, 0x2c, reg);
  36         need_reset = (reg != old_reg);
  37
  38         pnp_write_config(GPIO_DEV, 0x30, 0x0e);
  39         pnp_write_config(GPIO_DEV, 0xe0, 0xde);
  40         pnp_write_config(GPIO_DEV, 0xf0, 0xf3);
  41         pnp_write_config(GPIO_DEV, 0xf4, 0x80);
  42         pnp_write_config(GPIO_DEV, 0xf5, 0x80);
  43
  44         /* Invert GPIO33 */
  45         pnp_write_config(GPIO_DEV, 0xf2, 0x08);
  46
  47         reg = (bsel & 3) << 2;
  48         old_reg = pnp_read_config(GPIO_DEV, 0xf1);
  49         pnp_write_config(GPIO_DEV, 0xf1, reg);
  50         need_reset += ((reg & 0xc) != (old_reg & 0xc));
  51
  52         reg = (bsel >> 2) << 5;
  53         old_reg = pnp_read_config(GPIO_DEV, 0xe1);
  54         pnp_write_config(GPIO_DEV, 0xe1, reg);
  55         need_reset += ((reg & 0x20) != (old_reg & 0x20));
  56
  57         pnp_exit_ext_func_mode(GPIO_DEV);
  58
  59         return need_reset;
  60 }
  61
  62 static u8 msr_get_fsb(void)
  63 {
  64         u8 fsbcfg;
  65         msr_t msr;
  66         const u32 eax = cpuid_eax(1);
  67
  68         /* Netburst */
  69         if (((eax >> 8) & 0xf) == 0xf) {
  70                 msr = rdmsr(MSR_EBC_FREQUENCY_ID);
  71                 fsbcfg = (msr.lo >> 16) & 0x7;
  72         } else { /* Intel Core 2 */
  73                 msr = rdmsr(MSR_FSB_FREQ);
  74                 fsbcfg = msr.lo & 0x7;
  75         }
  76
  77         return fsbcfg;
  78 }
  79
  80 void mainboard_late_rcba_config(void)
  81 {
  82         /* Enable only PCIe Root Port Clock Gate */
  83         RCBA32(CG) = 0x00000001;
  84 }
  85
  86 void mainboard_pre_raminit_config(int s3_resume)
  87 {
  88         u8 c_bsel = msr_get_fsb();
  89         /*
  90          * Result is that FSB is incorrect on s3 resume (fixed at 800MHz).
  91          * Some CPU accept this others don't.
  92          */
  93         if (!s3_resume && setup_sio_gpio(c_bsel)) {
  94                 printk(BIOS_DEBUG,
  95                         "Needs reset to configure CPU BSEL straps\n");
  96                 full_reset();
  97         }
  98 }
  99
 100 void bootblock_mainboard_early_init(void)
 101 {
 102         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 103 }