src/mainboard/facebook/monolith/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef MAINBOARD_GPIO_H
   4 #define MAINBOARD_GPIO_H
   5
   6 #include <soc/gpio.h>
   7
   8 #ifndef __ACPI__
   9 /* Pad configuration in ramstage. */
  10 static const struct pad_config gpio_table[] = {
  11 /* PCH_RCIN# */         PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  12 /* LAD_0 */             PAD_CFG_NF(GPP_A1, DN_20K, DEEP, NF1),
  13 /* LAD_1 */             PAD_CFG_NF(GPP_A2, DN_20K, DEEP, NF1),
  14 /* LAD_2 */             PAD_CFG_NF(GPP_A3, DN_20K, DEEP, NF1),
  15 /* LAD_3 */             PAD_CFG_NF(GPP_A4, DN_20K, DEEP, NF1),
  16 /* LFRAME# */           PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  17 /* PCH_SERIRQ */        PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  18 /* PIRQA# */            PAD_CFG_GPO(GPP_A7, 1, DEEP),
  19 /* PM_CLKRUN_N */       PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  20 /* CLK_LPC_EC */        PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
  21 /* CLKOUT_LPC_CN */     PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
  22 /* SLEEP */             PAD_NC(GPP_A11, NONE),  /* available on the module not used here */
  23 /* NC */                PAD_NC(GPP_A12, NONE),
  24 /* PCH_SYSWARN */       PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  25 /* PM_SUS_STAT */       PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  26 /* KBC_SUSACK */        PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
  27 /* SD_1P8_SEL */        PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  28 /* SD_PWR_EN */         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  29 /* NC */                PAD_NC(GPP_A18, NONE),
  30 /* NC */                PAD_NC(GPP_A19, NONE),
  31 /* NC */                PAD_NC(GPP_A20, NONE),
  32 /* NC */                PAD_NC(GPP_A21, NONE),
  33 /* NC */                PAD_NC(GPP_A22, NONE),
  34 /* NC */                PAD_NC(GPP_A23, NONE),
  35 /* CORE_VID0 */         PAD_NC(GPP_B0, NONE),
  36 /* CORE_VID1 */         PAD_NC(GPP_B1, NONE),
  37 /* VRALERT# */          PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
  38 /* NC */                PAD_NC(GPP_B3, NONE),
  39 /* NC */                PAD_NC(GPP_B4, NONE),
  40 /* SRCCLKREQ0 */        PAD_NC(GPP_B5, NONE),
  41 /* SRCCLKREQ1 */        PAD_NC(GPP_B6, NONE),
  42 /* SRCCLKREQ2 */        PAD_NC(GPP_B7, NONE),
  43 /* SRCCLKREQ3 */        PAD_NC(GPP_B8, NONE),
  44 /* SRCCLKREQ4 */        PAD_NC(GPP_B9, NONE),
  45 /* SRCCLKREQ5 */        PAD_NC(GPP_B10, NONE),
  46 /* EXT_PWR_GATE */      PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  47 /* SLP_S0 */            PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  48 /* PCH_PLTRST */        PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  49 /* PCH_SPKR */          PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
  50 /* NC */                PAD_NC(GPP_B15, NONE),
  51 /* NC */                PAD_NC(GPP_B16, NONE),
  52 /* NC */                PAD_NC(GPP_B17, NONE),
  53 /* GSPI0_MOSI */        PAD_NC(GPP_B18, NONE),
  54 /* NC */                PAD_NC(GPP_B19, NONE),
  55 /* NC */                PAD_NC(GPP_B20, NONE),
  56 /* NC */                PAD_NC(GPP_B21, NONE),
  57 /* BIOS_SEL */          PAD_NC(GPP_B22, NONE),
  58 /* CB_OVT# */           PAD_CFG_GPO(GPP_B23, 1, DEEP),
  59
  60 /* SMB_SCL */           PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  61 /* SMB_SDA */           PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
  62 /* SMBALERT# */         PAD_CFG_GPO(GPP_C2, 1, DEEP),
  63 /* SML0_CLK */          PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
  64 /* SML0_SDA */          PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
  65 /* SML0_ALERT */        PAD_NC(GPP_C5, NONE),
  66 /* GPP_C6 - RESERVED */
  67 /* GPP_C7 - RESERVED */
  68 /* CPU_UART0_RXD */     PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
  69 /* CPU_UART0_TXD */     PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
  70 /* CPU_UART0_RTS */     PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
  71 /* CPU_UART0_CTS */     PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
  72 /* NC */                PAD_NC(GPP_C12, NONE),
  73 /* NC */                PAD_NC(GPP_C13, NONE),
  74 /* NC */                PAD_NC(GPP_C14, NONE),
  75 /* NC */                PAD_NC(GPP_C15, NONE),
  76 /* I2C0_SDA */          PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
  77 /* I2C0_SCL */          PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
  78 /* NC */                PAD_NC(GPP_C18, NONE),
  79 /* NC */                PAD_NC(GPP_C19, NONE),
  80 /* NC */                PAD_NC(GPP_C20, NONE),
  81 /* NC */                PAD_NC(GPP_C21, NONE),
  82 /* EC_SCI# NOT USED */  PAD_NC(GPP_C22, NONE),
  83 /* EC_SMI# NOT USED */  PAD_NC(GPP_C23, NONE),
  84 /* TOUCH_SPI1_CS */     PAD_NC(GPP_D0, NONE),
  85 /* TPM_PIRQ_N NOT USED */       PAD_NC(GPP_D1, NONE),
  86 /* NC */                PAD_NC(GPP_D2, NONE),
  87 /* NC */                PAD_NC(GPP_D3, NONE),
  88 /* NC */                PAD_NC(GPP_D4, NONE),
  89 /* NC */                PAD_NC(GPP_D5, NONE),
  90 /* NC */                PAD_NC(GPP_D6, NONE),
  91 /* NC */                PAD_NC(GPP_D7, NONE),
  92 /* NC */                PAD_NC(GPP_D8, NONE),
  93 /* NC */                PAD_NC(GPP_D9, NONE),
  94 /* NC */                PAD_NC(GPP_D11, NONE),
  95 /* NC */                PAD_NC(GPP_D12, NONE),
  96 /* NC */                PAD_NC(GPP_D13, NONE),
  97 /* NC */                PAD_NC(GPP_D14, NONE),
  98 /* NC */                PAD_NC(GPP_D15, NONE),
  99 /* NC */                PAD_NC(GPP_D16, NONE),
 100 /* NC */                PAD_NC(GPP_D17, NONE),
 101 /* NC */                PAD_NC(GPP_D18, NONE),
 102 /* NC */                PAD_NC(GPP_D19, NONE),
 103 /* NC */                PAD_NC(GPP_D20, NONE),
 104 /* LID# NOT USED */     PAD_NC(GPP_D21, NONE),
 105 /* NC */                PAD_NC(GPP_D22, NONE),
 106 /* NC */                PAD_NC(GPP_D23, NONE),
 107 /* NC */                PAD_NC(GPP_E0, NONE),
 108 /* NC */                PAD_NC(GPP_E1, NONE),
 109 /* NC */                PAD_NC(GPP_E2, NONE),
 110 /* NC */                PAD_NC(GPP_E3, NONE),
 111 /* DEVSLP0 TP */        PAD_NC(GPP_E4, NONE),
 112 /* DEVSLP0 TP */        PAD_NC(GPP_E5, NONE),
 113 /* DEVSLP1 TP */        PAD_NC(GPP_E6, NONE),
 114 /* NC */                PAD_NC(GPP_E7, NONE),
 115 /* SATA_LED_N */        PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 116 /* USB2_OC0_1 */        PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 117 /* USB2_OC2_3 */        PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 118 /* USB2_OC4_5 */        PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 119 /* USB2_OC6_7 */        PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 120 /* DDPB_HPD0_C */       PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 121 /* DDPC_HPD1_C */       PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 122 /* DDPD_HPD2_C NC */    PAD_NC(GPP_E15, NONE),
 123 /* DDPE_HPD3_C NC */    PAD_NC(GPP_E16, NONE),
 124 /* EDP_HPD_C */         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 125 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 126 /* DDPB_CTRLDAT */      PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 127 /* DDI2_DDC_SCL_L */    PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 128 /* DDI2_DDC_SDA_L */    PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
 129 /* DDPD_CTRLCLK NC */   PAD_NC(GPP_E22, NONE),
 130 /* DDPD_CTRLDAT NC */   PAD_NC(GPP_E23, NONE),
 131 /* NC */                PAD_NC(GPP_F0, NONE),
 132 /* NC */                PAD_NC(GPP_F1, NONE),
 133 /* NC */                PAD_NC(GPP_F2, NONE),
 134 /* NC */                PAD_NC(GPP_F3, NONE),
 135 /* NC */                PAD_NC(GPP_F4, NONE),
 136 /* NC */                PAD_NC(GPP_F5, NONE),
 137 /* NC */                PAD_NC(GPP_F6, NONE),
 138 /* NC */                PAD_NC(GPP_F7, NONE),
 139 /* NC */                PAD_NC(GPP_F8, NONE),
 140 /* NC */                PAD_NC(GPP_F9, NONE),
 141 /* NC */                PAD_NC(GPP_F10, NONE),
 142 /* NC */                PAD_NC(GPP_F11, NONE),
 143 /* EMMC_CMD */          PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 144 /* EMMC_DATA0 */        PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 145 /* EMMC_DATA1 */        PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 146 /* EMMC_DATA2 */        PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 147 /* EMMC_DATA3 */        PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 148 /* EMMC_DATA4 */        PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 149 /* EMMC_DATA5 */        PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 150 /* EMMC_DATA6 */        PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 151 /* EMMC_DATA7 */        PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 152 /* EMMC_STROBE */       PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 153 /* EMMC_CLK */          PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 154 /* GPP_F23 */           PAD_NC(GPP_F23, NONE),
 155 /* SD_CMD */            PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 156 /* SD_D0 */             PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 157 /* SD_D1 */             PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 158 /* SD_D2 */             PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 159 /* SD_D3 */             PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 160 /* SD_CD# */            PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
 161 /* SD_CLK */            PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 162 /* SD_WP */             PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
 163 /* PCH_BATLOW */        PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 164 /* KBC_ACPRESENT */     PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 165 /* PCH_LAN_WAKE */      PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 166 /* KBC_PWRBTN */        PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 167 /* SLP_S3# */           PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 168 /* SLP_S4# */           PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 169 /* PM_SLP_M_N */        PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 170 /* BIOS_RECOVERY NOT USED */    PAD_NC(GPD7, NONE),
 171 /* CPU_SUSCLK */        PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 172 /* SLP_WLAN# */         PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 173 /* SLP_S5# */           PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
 174 /* PCH_LANPHYC */       PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
 175 };
 176
 177 #endif
 178 #endif