mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / foxconn / g41s-k / hda_verb.c
blob40ab35d8fdaf3f38d7410a53de9d0b61caeb53db
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/azalia_device.h>
5 #if CONFIG(BOARD_FOXCONN_G41S_K)
6 const u32 cim_verb_data[] = {
7 /* coreboot specific header */
8 0x10ec0888, /* Vendor ID */
9 0x105b0dda, /* Subsystem ID */
10 0x0000000e, /* Number of entries */
12 /* Pin Widget Verb Table */
14 AZALIA_PIN_CFG(0, 0x11, 0x99430140),
15 AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
16 AZALIA_PIN_CFG(0, 0x14, 0x01014410),
17 AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
18 AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
19 AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
20 AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
21 AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
22 AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
23 AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
24 AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
25 AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
26 AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
27 AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
29 #else /* CONFIG_BOARD_FOXCONN_G41M */
30 const u32 cim_verb_data[] = {
31 /* coreboot specific header */
32 0x10ec0888, /* Vendor ID */
33 0x105b0dc0, /* Subsystem ID */
34 0x0000000e, /* Number of entries */
36 /* Pin Widget Verb Table */
38 AZALIA_PIN_CFG(2, 0x11, 0x01441140),
39 AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
40 AZALIA_PIN_CFG(2, 0x14, 0x01014410),
41 AZALIA_PIN_CFG(2, 0x15, 0x01011412),
42 AZALIA_PIN_CFG(2, 0x16, 0x01016411),
43 AZALIA_PIN_CFG(2, 0x17, 0x01012414),
44 AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
45 AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
46 AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
47 AZALIA_PIN_CFG(2, 0x1b, 0x02014c20),
48 AZALIA_PIN_CFG(2, 0x1c, 0x593301f0),
49 AZALIA_PIN_CFG(2, 0x1d, 0x4007f603),
50 AZALIA_PIN_CFG(2, 0x1e, 0x99430130),
51 AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
53 #endif
55 const u32 pc_beep_verbs[0] = {};
57 AZALIA_ARRAY_SIZES;