mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / gigabyte / ga-g41m-es2l / hda_verb.c
blob71e34125b4e9b127712788e43b4a93ce8e0d6aaf
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/azalia_device.h>
5 const u32 cim_verb_data[] = {
6 /* coreboot specific header */
7 0x10ec0887,
8 0x1458a002, // Subsystem ID
9 0x0000000e, // Number of entries
11 /* Pin Widget Verb Table */
13 AZALIA_PIN_CFG(0, 0x11, 0x411110f0),
14 AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
15 AZALIA_PIN_CFG(0, 0x14, 0x01014410),
16 AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
17 AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
18 AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
19 AZALIA_PIN_CFG(0, 0x18, 0x01a19c40),
20 AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
21 AZALIA_PIN_CFG(0, 0x1a, 0x0181344f),
22 AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
23 AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
24 AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
25 AZALIA_PIN_CFG(0, 0x1e, 0x014b6130),
26 AZALIA_PIN_CFG(0, 0x1f, 0x01cb7160),
29 const u32 pc_beep_verbs[0] = {};
31 AZALIA_ARRAY_SIZES;