mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / fatcat / dsdt.asl
blob03882c63276cd0926fa2d41f83754aaf402f06dc
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <acpi/acpi.h>
4 #include <variant/ec.h>
5 #include <variant/gpio.h>
7 DefinitionBlock(
8         "dsdt.aml",
9         "DSDT",
10         ACPI_DSDT_REV_2,
11         OEM_ID,
12         ACPI_TABLE_CREATOR,
13         0x20240917
16         #include <acpi/dsdt_top.asl>
17         #include <soc/intel/common/block/acpi/acpi/platform.asl>
19         /* global NVS and variables */
20         #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
22         #include <cpu/intel/common/acpi/cpu.asl>
24         Device (\_SB.PCI0) {
25                 #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
26                 #include <soc/intel/pantherlake/acpi/southbridge.asl>
27                 #include <soc/intel/pantherlake/acpi/tcss.asl>
28         }
30 #if CONFIG(EC_GOOGLE_CHROMEEC)
31         /* ChromeOS Embedded Controller */
32         Scope (\_SB.PCI0.LPCB)
33         {
34                 /* ACPI code for EC SuperIO functions */
35                 #include <ec/google/chromeec/acpi/superio.asl>
36                 /* ACPI code for EC functions */
37                 #include <ec/google/chromeec/acpi/ec.asl>
38         }
39 #endif
41         #include <southbridge/intel/common/acpi/sleepstates.asl>