mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / fatcat / ec.c
blobf828bc55477a0556fbb0a0e2286cd49566869b55
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <acpi/acpi.h>
4 #include <console/console.h>
5 #include <ec/ec.h>
6 #include <ec/google/chromeec/ec.h>
7 #include <variant/ec.h>
9 void mainboard_ec_init(void)
11 static const struct google_chromeec_event_info info = {
12 .log_events = MAINBOARD_EC_LOG_EVENTS,
13 .sci_events = MAINBOARD_EC_SCI_EVENTS,
14 .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
15 .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
16 .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
19 printk(BIOS_DEBUG, "mainboard: EC init\n");
21 google_chromeec_events_init(&info, acpi_is_wakeup_s3());