mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / herobrine / reset.c
blobd64c650b995751e183413a16bc78c215c0f96821
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <ec/google/chromeec/ec.h>
4 #include <reset.h>
6 /* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
7 but this works well enough for our purposes. */
8 void do_board_reset(void)
10 google_chromeec_reboot(EC_REBOOT_COLD, 0);