mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / peach_pit / devicetree.cb
blob636a8457487cad693802dbbba61a570f7ed78399
1 ## SPDX-License-Identifier: GPL-2.0-only
3 chip soc/samsung/exynos5420
4 device cpu_cluster 0 on end
5 register "xres" = "1366"
6 register "yres" = "768"
7 register "framebuffer_bits_per_pixel" = "16"
8 # complex magic timing!
9 register "clkval_f" = "2"
10 register "upper_margin" = "14"
11 register "lower_margin" = "3"
12 register "vsync" = "5"
13 register "left_margin" = "80"
14 register "right_margin" = "48"
15 register "hsync" = "32"
16 end