mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / zork / variants / dalboz / gpio.c
blob78b3a5a071cf8e97542eb0317045767f0039f1f7
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <gpio.h>
6 #include <ec/google/chromeec/ec.h>
8 /* This table is used by dalboz variant with board version < 2. */
9 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
10 /* DMIC_SEL */
11 PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
12 /* USB_OC2_L - USB A0 & A1 */
13 PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE),
14 /* TP */
15 PAD_NC(GPIO_32),
16 /* EN_PWR_TOUCHPAD_PS2 */
17 PAD_GPO(GPIO_67, HIGH),
18 /* EN_DEV_BEEP_L */
19 PAD_GPO(GPIO_89, HIGH),
20 /* USI_RESET */
21 PAD_GPO(GPIO_140, HIGH),
22 /* Unused */
23 PAD_NC(GPIO_143),
26 static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = {
27 /* DMIC_SEL */
28 PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
29 /* TP */
30 PAD_NC(GPIO_32),
31 /* EN_PWR_TOUCHPAD_PS2 */
32 PAD_GPO(GPIO_67, HIGH),
33 /* EN_DEV_BEEP_L */
34 PAD_GPO(GPIO_89, HIGH),
35 /* USI_RESET */
36 PAD_GPO(GPIO_140, HIGH),
39 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
41 uint32_t board_version;
44 * If board version cannot be read, assume that this is an older revision of the board
45 * and so apply overrides. If board version is provided by the EC, then apply overrides
46 * if version < 2.
48 if (google_chromeec_cbi_get_board_version(&board_version) != 0)
49 board_version = 1;
51 if (board_version < 2) {
52 *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
53 return bid_1_gpio_set_stage_ram;
54 } else if (board_version == 2) {
55 *size = ARRAY_SIZE(bid_2_gpio_set_stage_ram);
56 return bid_2_gpio_set_stage_ram;
59 *size = 0;
60 return NULL;