mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / zork / variants / gumboz / variant.c
blob81cadb6aec84c72bc479a9024fa372a00087be67
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/variants.h>
4 #include <device/device.h>
5 #include <drivers/i2c/generic/chip.h>
6 #include <soc/pci_devs.h>
7 #include <ec/google/chromeec/ec.h>
8 #include <ec/google/chromeec/i2c_tunnel/chip.h>
10 /* FIXME: Comments seem to suggest these are not entirely correct. */
11 static const fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = {
13 // DDI0, DP0, eDP
14 .connector_type = EDP,
15 .aux_index = AUX1,
16 .hdp_index = HDP1
19 // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub
20 .connector_type = DP,
21 .aux_index = AUX2,
22 .hdp_index = HDP2
25 // DP2 pins not connected on Dali
26 // DDI2, DP3, USB-C0
27 .connector_type = DP,
28 .aux_index = AUX4,
29 .hdp_index = HDP4,
33 void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
34 size_t *dxio_num,
35 const fsp_ddi_descriptor **ddi_descs,
36 size_t *ddi_num)
38 *dxio_descs = baseboard_get_dxio_descriptors(dxio_num);
39 *ddi_descs = &non_hdmi_ddi_descriptors[0];
40 *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors);