src/mainboard/ocp/deltalake/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pci_def.h>
   5 #include <device/pci_ops.h>
   6 #include <intelblocks/lpc_lib.h>
   7 #include <intelblocks/pcr.h>
   8 #include <soc/intel/common/block/lpc/lpc_def.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/pcr_ids.h>
  11 #include <superio/aspeed/ast2400/ast2400.h>
  12 #include <superio/aspeed/common/aspeed.h>
  13 #include <cpxsp_dl_gpio.h>
  14
  15 #define ASPEED_SIO_PORT 0x2E
  16 #define PCR_DMI_LPCIOD 0x2770
  17 #define PCR_DMI_LPCIOE 0x2774
  18
  19 static void enable_espi_lpc_io_windows(void)
  20 {
  21         /*
  22          * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
  23          * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
  24          * For that end it is wired into BMC virtual port.
  25          */
  26         uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
  27         uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
  28
  29         /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
  30         pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
  31         /* LPC I/O enable: com1 and com2 */
  32         pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
  33
  34         /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
  35         pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
  36         pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
  37 }
  38
  39 static uint8_t com_to_ast_sio(uint8_t com)
  40 {
  41         switch (com) {
  42         case 0:
  43                 return AST2400_SUART1;
  44         case 1:
  45                 return AST2400_SUART2;
  46         case 2:
  47                 return AST2400_SUART3;
  48         case 4:
  49                 return AST2400_SUART4;
  50         default:
  51                 return AST2400_SUART1;
  52         }
  53 }
  54
  55 void bootblock_mainboard_early_init(void)
  56 {
  57         /* pre-configure Lewisburg PCH GPIO pads */
  58         gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
  59
  60         /* Open IO windows */
  61         enable_espi_lpc_io_windows();
  62
  63         /* Configure appropriate physical port of SuperIO chip off BMC */
  64         const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT,
  65                 com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
  66         aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
  67 }