mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / ocp / deltalake / devicetree.cb
blob7d5839ed1d2f1bfdb5750302ab6bf37ea47b79b2
1 ## SPDX-License-Identifier: GPL-2.0-or-later
3 chip soc/intel/xeon_sp/cpx
5 register "pirqa_routing" = "PCH_IRQ11"
6 register "pirqb_routing" = "PCH_IRQ10"
7 register "pirqc_routing" = "PCH_IRQ11"
8 register "pirqd_routing" = "PCH_IRQ11"
9 register "pirqe_routing" = "PCH_IRQ11"
10 register "pirqf_routing" = "PCH_IRQ11"
11 register "pirqg_routing" = "PCH_IRQ11"
12 register "pirqh_routing" = "PCH_IRQ11"
14 # configure device interrupt routing
15 register "ir00_routing" = "0x3210" # IR00, Dev31
16 register "ir01_routing" = "0x3210" # IR01, Dev30
17 register "ir02_routing" = "0x3210" # IR02, Dev29
18 register "ir03_routing" = "0x3210" # IR03, Dev28
19 register "ir04_routing" = "0x3210" # IR04, Dev27
21 # configure interrupt polarity control
22 register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
23 register "ipc1" = "0x00000000" # IPC1
24 register "ipc2" = "0x00000000" # IPC2
25 register "ipc3" = "0x00000000" # IPC3
27 # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
28 # FB production turbo_ratio_limit is 0x1f1f1f2022222325
29 register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
30 # FB production turbo_ratio_limit_cores is 0x1c1812100c080402
31 register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
33 # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
34 register "pstate_req_ratio" = "0xa"
36 # configure VT-d
37 register "vtd_support" = "1"
38 register "x2apic" = "1"
40 register "gen1_dec" = "0x00fc0601" # BIC in-band update support
41 register "gen2_dec" = "0x000c0ca1" # IPMI KCS
43 # configure PCH PCIe port
44 register "pch_pci_port[8]" = "{
45 .ForceEnable = 0x1,
46 .PortLinkSpeed = PcieAuto,
49 register "cstate_states" = "CSTATES_C1C6"
51 device cpu_cluster 0 on end
53 device domain 0 on
54 device gpio 0 alias pch_gpio on end
55 device pci 00.0 on end # Host bridge
56 device pci 04.0 on end # Intel SkyLake-E CBDMA Registers
57 device pci 04.1 on end # Intel SkyLake-E CBDMA Registers
58 device pci 04.2 on end # Intel SkyLake-E CBDMA Registers
59 device pci 04.3 on end # Intel SkyLake-E CBDMA Registers
60 device pci 04.4 on end # Intel SkyLake-E CBDMA Registers
61 device pci 04.5 on end # Intel SkyLake-E CBDMA Registers
62 device pci 04.6 on end # Intel SkyLake-E CBDMA Registers
63 device pci 04.7 on end # Intel SkyLake-E CBDMA Registers
64 device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers
65 device pci 05.2 on end # Intel SkyLake-E RAS
66 device pci 05.4 on end # Intel SkyLake-E IOAPIC
67 device pci 07.0 on end
68 device pci 07.4 on end
69 device pci 07.7 on end
70 device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers
71 device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers
72 device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers
73 device pci 11.0 on end # Intel Device a26c: PCU
75 # PCH devices
76 device pci 11.5 on end # Intel C620 Series Chipset Family SSATA Controller [AHCI mode]
77 device pci 14.0 on end # Intel C620 Series Chipset Family USB 3.0 xHCI Controller
79 device pci 14.2 on end # Signal processing controller: Intel Device a231
80 device pci 16.0 on end # Communication controller: Intel Device a23a
81 device pci 16.1 on end # Communication controller: Intel Device a23b
82 device pci 16.4 on end # Communication controller: Intel Device a23e
83 device pci 17.0 on end # Intel C620 Series Chipset Family SATA Controller [AHCI mode]
84 device pci 1c.0 on end # PCI bridge: Intel Device a210
85 device pci 1c.4 on end # PCI bridge: Intel Device a214
86 device pci 1c.5 on end # PCI bridge: Intel Device a215
87 device pci 1d.0 on end # PCI bridge: Intel Device a218
88 device pci 1f.0 on
89 chip drivers/ipmi # BMC KCS
90 device pnp ca2.0 on end
91 use pch_gpio as gpio_dev
92 register "bmc_i2c_address" = "0x20"
93 register "bmc_boot_timeout" = "60"
94 register "post_complete_gpio" = "GPP_B20"
95 register "post_complete_invert" = "1"
96 end
97 chip drivers/ipmi/ocp # OCP specific IPMI porting
98 device pnp ca2.1 on end
99 end
100 chip drivers/pc80/tpm # TPM
101 device pnp 0c31.0 on end
103 end # ISA bridge: Intel Device a245
104 device pci 1f.1 on end # p2sb
105 device pci 1f.2 on end # Memory controller: Intel Device a221
106 device pci 1f.3 on end # Audio device: Intel Device a270
107 device pci 1f.4 on end # Intel C620 Series Chipset Family SMBus
108 device pci 1f.5 on end # Intel C620 Series Chipset Family SPI Controller