mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / siemens / mc_apl1 / bootblock.c
blob7aab2a0f07286ff06efd282732b0f93bbe697e1e
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <baseboard/variants.h>
4 #include <bootblock_common.h>
5 #include <device/pci_def.h>
6 #include <device/pci_ops.h>
7 #include <intelblocks/gpio.h>
8 #include <types.h>
10 static void pcie_rp_early_enable(void)
12 const pci_devfn_t rp_dev = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
13 CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
15 if (pci_read_config16(rp_dev, PCI_VENDOR_ID) == 0xffff)
16 return;
19 * Needs to be done "immediately after PERST# de-assertion"
20 * as per IAFW BIOS spec volume 2 (doc 559811)
22 pci_and_config32(rp_dev, 0x338, ~(1 << 26)); /* BLKDQDA */
23 pci_and_config32(rp_dev, 0xf4, ~(1 << 2)); /* BLKPLLEN */
26 void bootblock_mainboard_early_init(void)
28 const struct pad_config *pads;
29 size_t num;
31 pads = variant_early_gpio_table(&num);
32 gpio_configure_pads(pads, num);
34 /* Enable the PCIe root port when used before FSP-M MemoryInit() */
35 if (CONFIG(EARLY_PCI_BRIDGE))
36 pcie_rp_early_enable();