src/northbridge/intel/haswell/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H
   4 #define NORTHBRIDGE_INTEL_HASWELL_CHIP_H
   5
   6 #include <drivers/intel/gma/gma.h>
   7 #include <types.h>
   8
   9 struct peg_config {
  10         bool is_onboard;
  11         uint8_t power_limit_scale;
  12         uint8_t power_limit_value;
  13         uint16_t phys_slot_number;
  14 };
  15
  16 /*
  17  * Digital Port Hotplug Enable:
  18  *  0x04 = Enabled, 2ms   short pulse
  19  *  0x05 = Enabled, 4.5ms short pulse
  20  *  0x06 = Enabled, 6ms   short pulse
  21  *  0x07 = Enabled, 100ms short pulse
  22  */
  23 struct northbridge_intel_haswell_config {
  24         u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
  25         u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
  26         u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
  27
  28         /* IGD panel configuration */
  29         struct i915_gpu_panel_config panel_cfg;
  30
  31         struct peg_config peg_cfg[3];
  32
  33         bool gpu_ddi_e_connected;
  34
  35         bool ec_present;
  36
  37         bool dq_pins_interleaved;
  38
  39         bool usb_xhci_on_resume;
  40
  41         struct i915_gpu_controller_info gfx;
  42
  43         u8 spd_addresses[4];
  44 };
  45
  46 #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */