mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / northbridge / intel / haswell / raminit.h
blob6c76739e77834056f74a4c5974519d864e2ab09e
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
4 #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
6 #include <types.h>
7 #include "chip.h"
9 #define SPD_MEMORY_DOWN 0xff
11 struct spd_info {
12 uint8_t addresses[4];
13 unsigned int spd_index;
16 /* Mainboard callback to fill in the SPD addresses */
17 void mb_get_spd_map(struct spd_info *spdi);
19 void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg);
20 void perform_raminit(const int s3resume);
22 #endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */