mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / northbridge / intel / ironlake / Kconfig
blob2bafebf92e1444a8038476ccd9a487305e4ebfe7
1 # SPDX-License-Identifier: GPL-2.0-only
3 config NORTHBRIDGE_INTEL_IRONLAKE
4         bool
5         select CPU_INTEL_MODEL_2065X
6         select VGA
7         select INTEL_EDID
8         select INTEL_GMA_ACPI
9         select CACHE_MRC_SETTINGS
10         select HAVE_DEBUG_RAM_SETUP
11         select USE_DDR3
12         select NEED_SMALL_2MB_PAGE_TABLES
14 if NORTHBRIDGE_INTEL_IRONLAKE
16 config VBOOT
17         select VBOOT_MUST_REQUEST_DISPLAY
18         select VBOOT_STARTS_IN_BOOTBLOCK
19         # CPU is reset without platform/TPM during romstage
20         select TPM_STARTUP_IGNORE_POSTINIT
22 config CBFS_SIZE
23         default 0x100000
25 config VGA_BIOS_ID
26         string
27         default "8086,0046"
29 config DCACHE_RAM_BASE
30         hex
31         default 0xfefc0000
33 config DCACHE_RAM_SIZE
34         hex
35         default 0x10000
37 config DCACHE_BSP_STACK_SIZE
38         hex
39         default 0x2000
40         help
41           The amount of anticipated stack usage in CAR by bootblock and
42           other stages.
44 config ECAM_MMCONF_BASE_ADDRESS
45         default 0xe0000000
47 config ECAM_MMCONF_BUS_NUMBER
48         default 256
50 # This number must be equal or lower than what's reported in ACPI PCI _CRS
51 config DOMAIN_RESOURCE_32BIT_LIMIT
52         default 0xfec00000
54 config INTEL_GMA_BCLV_OFFSET
55         default 0x48254
57 config FIXED_MCHBAR_MMIO_BASE
58         default 0xfed10000
60 config FIXED_DMIBAR_MMIO_BASE
61         default 0xfed18000
63 config FIXED_EPBAR_MMIO_BASE
64         default 0xfed19000
66 endif