mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / northbridge / intel / ironlake / smi.c
blob0604d13155ba77009d971383cb8f836df5ab8cf7
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #define __SIMPLE_DEVICE__
5 #include <types.h>
6 #include <device/device.h>
7 #include <device/pci_ops.h>
8 #include "ironlake.h"
10 #include <cpu/intel/smm_reloc.h>
12 void northbridge_write_smram(u8 smram)
14 pci_write_config8(QPI_SAD, QPD0F1_SMRAM, smram);