mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / northbridge / intel / sandybridge / pcie.c
blob244b0f5a40ac52d3bb006b06dbc113a74151819e
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pciexp.h>
6 #include <device/pci_ids.h>
7 #include <assert.h>
9 static const char *pcie_acpi_name(const struct device *dev)
11 assert(dev);
13 if (dev->path.type != DEVICE_PATH_PCI)
14 return NULL;
16 assert(dev->upstream);
17 if (dev->upstream->secondary == 0)
18 switch (dev->path.pci.devfn) {
19 case PCI_DEVFN(1, 0):
20 return "PEGP";
21 case PCI_DEVFN(1, 1):
22 return "PEG1";
23 case PCI_DEVFN(1, 2):
24 return "PEG2";
25 case PCI_DEVFN(6, 0):
26 return "PEG6";
29 struct device *const port = dev->upstream->dev;
30 assert(port);
31 assert(port->upstream);
33 if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
34 port->upstream->secondary == 0 &&
35 (port->path.pci.devfn == PCI_DEVFN(1, 0) ||
36 port->path.pci.devfn == PCI_DEVFN(1, 1) ||
37 port->path.pci.devfn == PCI_DEVFN(1, 2) ||
38 port->path.pci.devfn == PCI_DEVFN(6, 0)))
39 return "DEV0";
41 return NULL;
44 static struct device_operations device_ops = {
45 .read_resources = pci_bus_read_resources,
46 .set_resources = pci_dev_set_resources,
47 .enable_resources = pci_bus_enable_resources,
48 .scan_bus = pciexp_scan_bridge,
49 .reset_bus = pci_bus_reset,
50 .init = pci_dev_init,
51 .ops_pci = &pci_dev_ops_pci,
52 .acpi_name = pcie_acpi_name,
55 static const unsigned short pci_device_ids[] = {
56 0x0101, 0x0105, 0x0109, 0x010d,
57 0x0151, 0x0155, 0x0159, 0x015d,
61 static const struct pci_driver pch_pcie __pci_driver = {
62 .ops = &device_ops,
63 .vendor = PCI_VID_INTEL,
64 .devices = pci_device_ids,