mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801dx / ac97.c
blobc30c5ef317bc092c5204d0ad678b95dfa6357b7f
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/io.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ids.h>
9 #include <device/pci_ops.h>
10 #include <stdint.h>
12 #include "i82801dx.h"
14 #define NAMBAR 0x10
15 #define MASTER_VOL 0x02
16 #define PAGING 0x24
17 #define EXT_AUDIO 0x28
18 #define FUNC_SEL 0x66
19 #define INFO_IO 0x68
20 #define CONNECTOR 0x6a
21 #define VENDOR_ID1 0x7c
22 #define VENDOR_ID2 0x7e
23 #define SEC_VENDOR_ID1 0xfc
24 #define SEC_VENDOR_ID2 0xfe
26 #define NABMBAR 0x14
27 #define GLOB_CNT 0x2c
28 #define GLOB_STA 0x30
29 #define CAS 0x34
31 #define MMBAR 0x10
32 #define EXT_MODEM_ID1 0x3c
33 #define EXT_MODEM_ID2 0xbc
35 #define MBAR 0x14
36 #define SEC_CODEC 0x40
38 /* FIXME. This table is probably mainboard specific */
39 static u16 ac97_function[16*2][4] = {
40 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
41 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
42 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
43 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
44 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
45 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
46 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
47 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
48 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
49 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
50 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
51 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
52 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
53 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
54 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
55 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
56 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
57 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
58 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
59 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
60 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
61 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
62 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
63 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
64 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
65 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
66 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
67 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
68 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
69 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
70 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
71 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) }
74 static u16 nabmbar;
75 static u16 nambar;
77 static int ac97_semaphore(void)
79 int timeout;
80 u8 reg8;
82 timeout = 0xffff;
83 do {
84 reg8 = inb(nabmbar + CAS);
85 timeout--;
86 } while ((reg8 & 1) && timeout);
87 if (!timeout)
88 printk(BIOS_DEBUG, "Timeout!\n");
90 return (!timeout);
93 static void init_cnr(void)
95 // TODO
98 static void program_sigid(struct device *dev, u32 id)
100 pci_write_config32(dev, 0x2c, id);
103 static void ac97_audio_init(struct device *dev)
105 u16 reg16;
106 u32 reg32;
107 int i;
109 printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
111 /* top 16 bits are zero, so don't read them */
112 nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
113 nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;
115 reg16 = inw(nabmbar + GLOB_CNT);
116 reg16 |= (1 << 1); /* Remove AC_RESET# */
117 outw(reg16, nabmbar + GLOB_CNT);
119 /* Wait 600ms. Ouch. */
120 udelay(600 * 1000);
122 init_cnr();
124 /* Detect Primary AC'97 Codec */
125 reg32 = inl(nabmbar + GLOB_STA);
126 if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
127 /* Primary Codec not found */
128 printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
129 return;
132 ac97_semaphore();
134 /* Detect if codec is programmable */
135 outw(0x8000, nambar + MASTER_VOL);
136 ac97_semaphore();
137 if (inw(nambar + MASTER_VOL) != 0x8000) {
138 printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
139 return;
142 /* Program Vendor IDs */
143 reg32 = inw(nambar + VENDOR_ID1);
144 reg32 <<= 16;
145 reg32 |= (u16)inw(nambar + VENDOR_ID2);
147 program_sigid(dev, reg32);
149 /* Is Codec AC'97 2.3 compliant? */
150 reg16 = inw(nambar + EXT_AUDIO);
151 /* [11:10] = 10b -> AC'97 2.3 */
152 if ((reg16 & 0x0c00) != 0x0800) {
153 /* No 2.3 Codec. We're done */
154 return;
157 /* Select Page 1 */
158 reg16 = inw(nambar + PAGING);
159 reg16 &= 0xfff0;
160 reg16 |= 0x0001;
161 outw(reg16, nambar + PAGING);
163 for (i = 0x0a * 2; i > 0; i--) {
164 outw(i, nambar + FUNC_SEL);
166 /* Function could not be selected. Next one */
167 if (inw(nambar + FUNC_SEL) != i)
168 continue;
170 reg16 = inw(nambar + INFO_IO);
172 /* Function Information present? */
173 if (!(reg16 & (1 << 0)))
174 continue;
176 /* Function Information valid? */
177 if (!(reg16 & (1 << 4)))
178 continue;
180 /* Program Buffer Delay [9:5] */
181 reg16 &= 0x03e0;
182 reg16 |= ac97_function[i][0];
184 /* Program Gain [15:11] */
185 reg16 |= ac97_function[i][1];
187 /* Program Inversion [10] */
188 reg16 |= ac97_function[i][2];
190 outw(reg16, nambar + INFO_IO);
192 /* Program Connector / Jack Location */
193 reg16 = inw(nambar + CONNECTOR);
194 reg16 &= 0x1fff;
195 reg16 |= ac97_function[i][3];
196 outw(reg16, nambar + CONNECTOR);
200 static void ac97_modem_init(struct device *dev)
202 u16 reg16;
203 u32 reg32;
204 u16 mmbar, mbar;
206 mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;
207 mbar = pci_read_config16(dev, MBAR) & 0xfffe;
209 reg16 = inw(mmbar + EXT_MODEM_ID1);
210 if ((reg16 & 0xc000) != 0xc000) {
211 if (reg16 & (1 << 0)) {
212 reg32 = inw(mmbar + VENDOR_ID2);
213 reg32 <<= 16;
214 reg32 |= (u16)inw(mmbar + VENDOR_ID1);
215 program_sigid(dev, reg32);
216 return;
220 /* Secondary codec? */
221 reg16 = inw(mbar + SEC_CODEC);
222 if ((reg16 & (1 << 9)) == 0)
223 return;
225 reg16 = inw(mmbar + EXT_MODEM_ID2);
226 if ((reg16 & 0xc000) == 0x4000) {
227 if (reg16 & (1 << 0)) {
228 reg32 = inw(mmbar + SEC_VENDOR_ID2);
229 reg32 <<= 16;
230 reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);
231 program_sigid(dev, reg32);
232 return;
237 static struct device_operations ac97_audio_ops = {
238 .read_resources = pci_dev_read_resources,
239 .set_resources = pci_dev_set_resources,
240 .enable_resources = pci_dev_enable_resources,
241 .enable = i82801dx_enable,
242 .init = ac97_audio_init,
245 static struct device_operations ac97_modem_ops = {
246 .read_resources = pci_dev_read_resources,
247 .set_resources = pci_dev_set_resources,
248 .enable_resources = pci_dev_enable_resources,
249 .enable = i82801dx_enable,
250 .init = ac97_modem_init,
253 /* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
254 static const struct pci_driver i82801db_ac97_audio __pci_driver = {
255 .ops = &ac97_audio_ops,
256 .vendor = PCI_VID_INTEL,
257 .device = PCI_DID_INTEL_82801DB_AC97_AUDIO,
260 static const struct pci_driver i82801db_ac97_modem __pci_driver = {
261 .ops = &ac97_modem_ops,
262 .vendor = PCI_VID_INTEL,
263 .device = PCI_DID_INTEL_82801DB_AC97_MODEM,