mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801dx / chip.h
blob50f4f1c9981bd3f679ddbd9b31c20d62748f30a4
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef I82801DX_CHIP_H
4 #define I82801DX_CHIP_H
6 #include <stdint.h>
8 struct southbridge_intel_i82801dx_config {
9 int enable_usb;
10 int enable_native_ide;
11 /**
12 * Interrupt Routing configuration
13 * If bit7 is 1, the interrupt is disabled.
15 uint8_t pirqa_routing;
16 uint8_t pirqb_routing;
17 uint8_t pirqc_routing;
18 uint8_t pirqd_routing;
19 uint8_t pirqe_routing;
20 uint8_t pirqf_routing;
21 uint8_t pirqg_routing;
22 uint8_t pirqh_routing;
24 uint8_t ide0_enable;
25 uint8_t ide1_enable;
28 #endif /* I82801DX_CHIP_H */