src/southbridge/intel/i82801gx/azalia.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/pci_ops.h>
   8 #include <device/mmio.h>
   9 #include <delay.h>
  10 #include <device/azalia_device.h>
  11 #include <types.h>
  12
  13 #include "chip.h"
  14 #include "i82801gx.h"
  15
  16 static int codec_detect(u8 *base)
  17 {
  18         u32 reg32;
  19
  20         if (azalia_enter_reset(base) != CB_SUCCESS)
  21                 goto no_codec;
  22
  23         if (azalia_exit_reset(base) != CB_SUCCESS)
  24                 goto no_codec;
  25
  26         /* Read in Codec location (BAR + 0xe)[2..0] */
  27         reg32 = read32(base + HDA_STATESTS_REG);
  28         reg32 &= 0x0f;
  29         if (!reg32)
  30                 goto no_codec;
  31
  32         return reg32;
  33
  34 no_codec:
  35         /* Codec not found, put HDA back in reset */
  36         azalia_enter_reset(base);
  37         printk(BIOS_DEBUG, "Azalia: No codec!\n");
  38         return 0;
  39 }
  40
  41 static void azalia_init(struct device *dev)
  42 {
  43         u8 *base;
  44         struct resource *res;
  45         u32 codec_mask;
  46         u8 reg8;
  47
  48         // ESD
  49         pci_update_config32(dev, 0x134, ~(0xff << 16), 2 << 16);
  50
  51         // Link1 description
  52         pci_update_config32(dev, 0x140, ~(0xff << 16), 2 << 16);
  53
  54         // Port VC0 Resource Control Register
  55         pci_update_config32(dev, 0x114, ~(0xff << 0), 1);
  56
  57         // VCi traffic class
  58         pci_or_config8(dev, 0x44, 7 << 0); // TC7
  59
  60         // VCi Resource Control
  61         pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */
  62
  63         /* Set Bus Master */
  64         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
  65
  66         pci_write_config8(dev, 0x3c, 0x0a); // unused?
  67
  68         // TODO Actually check if we're AC97 or HDA instead of hardcoding this
  69         // here, in devicetree.cb and/or romstage.c.
  70         reg8 = pci_read_config8(dev, 0x40);
  71         reg8 |= (1 << 3); // Clear Clock Detect Bit
  72         pci_write_config8(dev, 0x40, reg8);
  73         reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
  74         pci_write_config8(dev, 0x40, reg8);
  75         reg8 |= (1 << 2); // Enable clock detection
  76         pci_write_config8(dev, 0x40, reg8);
  77         mdelay(1);
  78         reg8 = pci_read_config8(dev, 0x40);
  79         printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
  80
  81         // Select Azalia mode. This needs to be controlled via devicetree.cb
  82         pci_or_config8(dev, 0x40, 1); // Audio Control
  83
  84         // Docking not supported
  85         pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
  86
  87         res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  88         if (!res)
  89                 return;
  90
  91         // NOTE this will break as soon as the Azalia gets a bar above 4G.
  92         // Is there anything we can do about it?
  93         base = res2mmio(res, 0, 0);
  94         printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base);
  95         codec_mask = codec_detect(base);
  96
  97         if (codec_mask) {
  98                 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
  99                 azalia_codecs_init(base, codec_mask);
 100         }
 101 }
 102
 103 static struct device_operations azalia_ops = {
 104         .read_resources         = pci_dev_read_resources,
 105         .set_resources          = pci_dev_set_resources,
 106         .enable_resources       = pci_dev_enable_resources,
 107         .init                   = azalia_init,
 108         .enable                 = i82801gx_enable,
 109         .ops_pci                = &pci_dev_ops_pci,
 110 };
 111
 112 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
 113 static const struct pci_driver i82801gx_azalia __pci_driver = {
 114         .ops    = &azalia_ops,
 115         .vendor = PCI_VID_INTEL,
 116         .device = 0x27d8,
 117 };