mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801gx / smbus.c
blobf26ddd48030edf2efb80afd585b5443c521cb842
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/device.h>
4 #include <device/smbus.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/smbus_host.h>
8 #include <southbridge/intel/common/smbus_ops.h>
9 #include "i82801gx.h"
11 static struct device_operations smbus_ops = {
12 .read_resources = smbus_read_resources,
13 .set_resources = pci_dev_set_resources,
14 .enable_resources = pci_dev_enable_resources,
15 .scan_bus = scan_smbus,
16 .enable = i82801gx_enable,
17 .ops_smbus_bus = &lops_smbus_bus,
18 .ops_pci = &pci_dev_ops_pci,
21 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
22 static const struct pci_driver i82801gx_smbus __pci_driver = {
23 .ops = &smbus_ops,
24 .vendor = PCI_VID_INTEL,
25 .device = 0x27da,