mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801ix / Kconfig
blob21bc02b8277292f2e72bef3490ed4bd20d1da0de
1 # SPDX-License-Identifier: GPL-2.0-only
3 config SOUTHBRIDGE_INTEL_I82801IX
4         bool
5         select ACPI_COMMON_MADT_IOAPIC
6         select ACPI_COMMON_MADT_LAPIC
7         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
8         select ACPI_SOC_NVS
9         select AZALIA_HDA_CODEC_SUPPORT
10         select HAVE_SMI_HANDLER if !NO_SMM
11         select HAVE_USBDEBUG_OPTIONS
12         select INTEL_DESCRIPTOR_MODE_CAPABLE
13         select SOUTHBRIDGE_INTEL_COMMON_GPIO
14         select SOUTHBRIDGE_INTEL_COMMON_PMBASE
15         select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
16         select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
17         select SOUTHBRIDGE_INTEL_COMMON_RESET
18         select SOUTHBRIDGE_INTEL_COMMON_RTC
19         select SOUTHBRIDGE_INTEL_COMMON_SMBUS
20         select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
21         select SOUTHBRIDGE_INTEL_COMMON_SMM if !NO_SMM
22         select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35
23         select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
24         select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
25         select TCO_SPACE_NOT_YET_SPLIT
26         select USE_WATCHDOG_ON_BOOT
28 if SOUTHBRIDGE_INTEL_I82801IX
30 config EHCI_BAR
31         hex
32         default 0xfef00000
34 config HPET_MIN_TICKS
35         default 0x80
37 ## Some enterprise variants may require an IFD
38 config INTEL_DESCRIPTOR_MODE_REQUIRED
39         bool
40         default n
42 config PCIEXP_HOTPLUG
43         default y
45 endif