src/southbridge/intel/i82801ix/i82801ix.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_I82801IX_I82801IX_H
   4 #define SOUTHBRIDGE_INTEL_I82801IX_I82801IX_H
   5
   6 #define DEFAULT_TBAR            ((u8 *)0xfed1b000)
   7
   8 #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */
   9
  10 #if CONFIG(BOARD_EMULATION_QEMU_X86_Q35)
  11 /*
  12  * Qemu has the fw_cfg interface at 0x510.  Move the pmbase to a
  13  * non-conflicting address.  No need to worry about speedstep, it
  14  * is not supported by qemu and isn't enabled in the qemu config.
  15  */
  16 # define DEFAULT_PMBASE         0x00000600
  17 #else
  18 # define DEFAULT_PMBASE         0x00000500 /* Speedstep code has this hardcoded, too. */
  19 #endif
  20 #define DEFAULT_TCOBASE         (DEFAULT_PMBASE + 0x60)
  21 #define DEFAULT_GPIOBASE        0x00000580
  22
  23 #define GP_IO_USE_SEL   0x00
  24 #define GP_IO_SEL       0x04
  25 #define GP_LVL          0x0c
  26 #define GPO_BLINK       0x18
  27 #define GPI_INV         0x2c
  28 #define GP_IO_USE_SEL2  0x30
  29 #define GP_IO_SEL2      0x34
  30 #define GP_LVL2         0x38
  31
  32 #define MAINBOARD_POWER_OFF     0
  33 #define MAINBOARD_POWER_ON      1
  34 #define MAINBOARD_POWER_KEEP    2
  35
  36 /* D31:F0 LPC bridge */
  37 #define D31F0_ACPI_CNTL         0x44
  38 #define D31F0_GPIO_BASE         0x48
  39 #define D31F0_GPIO_CNTL         0x4c
  40 #define D31F0_PIRQA_ROUT        0x60
  41 #define D31F0_PIRQB_ROUT        0x61
  42 #define D31F0_PIRQC_ROUT        0x62
  43 #define D31F0_PIRQD_ROUT        0x63
  44 #define D31F0_SERIRQ_CNTL       0x64
  45 #define D31F0_PIRQE_ROUT        0x68
  46 #define D31F0_PIRQF_ROUT        0x69
  47 #define D31F0_PIRQG_ROUT        0x6a
  48 #define D31F0_PIRQH_ROUT        0x6b
  49 #define D31F0_LPC_IODEC         0x80
  50 #define D31F0_LPC_EN            0x82
  51 #define   CNF2_LPC_EN           (1 << 13) /* 0x4e/0x4f */
  52 #define   CNF1_LPC_EN           (1 << 12) /* 0x2e/0x2f */
  53 #define   MC_LPC_EN             (1 << 11) /* 0x62/0x66 */
  54 #define   KBC_LPC_EN            (1 << 10) /* 0x60/0x64 */
  55 #define   GAMEH_LPC_EN          (1 << 9)  /* 0x208/0x20f */
  56 #define   GAMEL_LPC_EN          (1 << 8)  /* 0x200/0x207 */
  57 #define   FDD_LPC_EN            (1 << 3)  /* LPC_IO_DEC[12] */
  58 #define   LPT_LPC_EN            (1 << 2)  /* LPC_IO_DEC[9:8] */
  59 #define   COMB_LPC_EN           (1 << 1)  /* LPC_IO_DEC[6:4] */
  60 #define   COMA_LPC_EN           (1 << 0)  /* LPC_IO_DEC[2:0] */
  61 #define D31F0_GEN1_DEC          0x84
  62 #define D31F0_GEN2_DEC          0x88
  63 #define D31F0_GEN3_DEC          0x8c
  64 #define D31F0_GEN4_DEC          0x90
  65 #define D31F0_C5_EXIT_TIMING    0xa8
  66 #define D31F0_CxSTATE_CNF       0xa9
  67 #define D31F0_C4TIMING_CNT      0xaa
  68
  69 /* D31:F2 SATA */
  70 #define D31F2_IDE_TIM_PRI       0x40
  71 #define D31F2_IDE_TIM_SEC       0x42
  72 #define D31F2_SIDX              0xa0
  73 #define D31F2_SDAT              0xa4
  74
  75 /* D30:F0 PCI-to-PCI bridge */
  76 #define D30F0_SMLT              0x1b
  77
  78 /* D28:F0-5 PCIe root ports */
  79 #define D28Fx_XCAP              0x42
  80 #define D28Fx_SLCAP             0x54
  81
  82 /* PCI Configuration Space (D31:F3): SMBus */
  83 #define SMB_BASE                0x20
  84 #define HOSTC                   0x40
  85
  86 /* HOSTC bits */
  87 #define I2C_EN                  (1 << 2)
  88 #define SMB_SMI_EN              (1 << 1)
  89 #define HST_EN                  (1 << 0)
  90
  91 #define RCBA_V0CTL              0x0014
  92 #define RCBA_V1CAP              0x001c
  93 #define RCBA_V1CTL              0x0020
  94 #define RCBA_V1STS              0x0026
  95 #define RCBA_PAT                0x0030
  96 #define RCBA_CIR1               0x0088
  97 #define RCBA_ESD                0x0104
  98 #define RCBA_ULD                0x0110
  99 #define RCBA_ULBA               0x0118
 100 #define RCBA_LCAP               0x01a4
 101 #define RCBA_LCTL               0x01a8
 102 #define RCBA_LSTS               0x01aa
 103 #define RCBA_CIR2               0x01f4
 104 #define RCBA_CIR3               0x01fc
 105 #define RCBA_BCR                0x0220
 106 #define RCBA_DMIC               0x0234
 107 #define RCBA_RPFN               0x0238
 108 #define RCBA_CIR13              0x0f20
 109 #define RCBA_CIR5               0x1d40
 110 #define RCBA_DMC                0x2010
 111 #define RCBA_CIR6               0x2024
 112 #define RCBA_CIR7               0x2034
 113 #define RCBA_HPTC               0x3404
 114 #define GCS                     0x3410
 115 #define RCBA_BUC                0x3414
 116 #define RCBA_FD                 0x3418 /* Function Disable, see below. */
 117 #define RCBA_CG                 0x341c
 118 #define RCBA_FDSW               0x3420
 119 #define RCBA_CIR8               0x3430
 120 #define RCBA_CIR9               0x350c
 121 #define RCBA_CIR10              0x352c
 122 #define RCBA_MAP                0x35f0 /* UHCI controller #6 remapping */
 123
 124 #define BUC_LAND        (1 <<  5) /* LAN */
 125 #define FD_SAD2         (1 << 25) /* SATA #2 */
 126 #define FD_TTD          (1 << 24) /* Thermal Throttle */
 127 #define FD_PE6D         (1 << 21) /* PCIe root port 6 */
 128 #define FD_PE5D         (1 << 20) /* PCIe root port 5 */
 129 #define FD_PE4D         (1 << 19) /* PCIe root port 4 */
 130 #define FD_PE3D         (1 << 18) /* PCIe root port 3 */
 131 #define FD_PE2D         (1 << 17) /* PCIe root port 2 */
 132 #define FD_PE1D         (1 << 16) /* PCIe root port 1 */
 133 #define FD_EHCI1D       (1 << 15) /* EHCI #1 */
 134 #define FD_LBD          (1 << 14) /* LPC bridge */
 135 #define FD_EHCI2D       (1 << 13) /* EHCI #2 */
 136 #define FD_U5D          (1 << 12) /* UHCI #5 */
 137 #define FD_U4D          (1 << 11) /* UHCI #4 */
 138 #define FD_U3D          (1 << 10) /* UHCI #3 */
 139 #define FD_U2D          (1 <<  9) /* UHCI #2 */
 140 #define FD_U1D          (1 <<  8) /* UHCI #1 */
 141 #define FD_U6D          (1 <<  7) /* UHCI #6 */
 142 #define FD_HDAD         (1 <<  4) /* HD audio */
 143 #define FD_SD           (1 <<  3) /* SMBus */
 144 #define FD_SAD1         (1 <<  2) /* SATA #1 */
 145
 146 #ifndef __ACPI__
 147
 148 #include <device/pci_ops.h>
 149
 150 static inline int lpc_is_mobile(const u16 devid)
 151 {
 152         return (devid == 0x2917) || (devid == 0x2919);
 153 }
 154 #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
 155
 156 void aseg_smm_lock(void);
 157
 158 void i82801ix_early_init(void);
 159 void i82801ix_lpc_setup(void);
 160 void i82801ix_dmi_setup(void);
 161 void i82801ix_dmi_poll_vc1(void);
 162
 163 #endif
 164
 165 #endif