soc/intel/xeon_sp: Align resources to 4K
[coreboot2.git] / configs / config.portwell_m107.debug_smmstore_oxpcie_em100spi
blob0861af3891f246b199054fc4c5f94baff1734c3d
1 # Not meant for actual use, but rather to build-test individual options.
2 # If keeping this combination of options buildable becomes too hard in
3 # the future, then this config can be split into several smaller chunks.
4 # Exercises, among other things:
5 # + SMMSTORE
6 # + OXPCIE support
7 # + FSP MP init
8 # + EM100Pro SPI console
9 # + Debug options
10 CONFIG_VENDOR_PORTWELL=y
11 CONFIG_BOARD_PORTWELL_M107=y
12 CONFIG_CONSOLE_POST=y
13 # CONFIG_CONSOLE_SERIAL is not set
14 CONFIG_ENABLE_BUILTIN_COM1=y
15 CONFIG_ONBOARD_MEM_KINGSTON=y
16 CONFIG_USE_INTEL_FSP_MP_INIT=y
17 CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y
18 CONFIG_SOC_INTEL_DEBUG_CONSENT=y
19 CONFIG_PCIEXP_HOTPLUG=y
20 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
21 CONFIG_SOFTWARE_I2C=y
22 CONFIG_SMMSTORE=y
23 CONFIG_SPI_FLASH_NO_FAST_READ=y
24 CONFIG_DRIVERS_UART_OXPCIE=y
25 CONFIG_DRIVERS_GENESYSLOGIC_GL9755=y
26 CONFIG_DISPLAY_HOBS=y
27 CONFIG_DISPLAY_VBT=y
28 CONFIG_DISPLAY_FSP_ENTRY_POINTS=y
29 CONFIG_DISPLAY_UPD_DATA=y
30 CONFIG_EM100PRO_SPI_CONSOLE=y
31 CONFIG_DISPLAY_MTRRS=y
32 CONFIG_GDB_STUB=y
33 CONFIG_GDB_WAIT=y
34 CONFIG_FATAL_ASSERTS=y
35 CONFIG_DEBUG_CBFS=y
36 CONFIG_DEBUG_SMBUS=y
37 CONFIG_DEBUG_SMI=y
38 CONFIG_DEBUG_PERIODIC_SMI=y
39 CONFIG_DEBUG_MALLOC=y
40 CONFIG_DEBUG_CONSOLE_INIT=y
41 CONFIG_REALMODE_DEBUG=y
42 CONFIG_DEBUG_BOOT_STATE=y