src/mainboard/samsung/stumpy/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <stdint.h>
   5 #include <pc80/mc146818rtc.h>
   6 #include <bootmode.h>
   7 #include <superio/ite/common/ite.h>
   8 #include <superio/ite/common/ite_gpio.h>
   9 #include <superio/ite/it8772f/it8772f.h>
  10 #include <northbridge/intel/sandybridge/sandybridge.h>
  11 #include <northbridge/intel/sandybridge/raminit.h>
  12 #include <southbridge/intel/bd82x6x/pch.h>
  13 #include <southbridge/intel/common/gpio.h>
  14 #include <superio/smsc/lpc47n207/lpc47n207.h>
  15
  16 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
  17 #define GPIO_DEV   PNP_DEV(0x2e, IT8772F_GPIO)
  18 #define EC_DEV     PNP_DEV(0x2e, IT8772F_EC)
  19
  20 void mainboard_late_rcba_config(void)
  21 {
  22         /*
  23          *             GFX    INTA -> PIRQA (MSI)
  24          * D28IP_P1IP  WLAN   INTA -> PIRQB
  25          * D28IP_P4IP  ETH0   INTB -> PIRQC
  26          * D29IP_E1P   EHCI1  INTA -> PIRQD
  27          * D26IP_E2P   EHCI2  INTA -> PIRQE
  28          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  29          * D31IP_SMIP  SMBUS  INTB -> PIRQG
  30          * D31IP_TTIP  THRT   INTC -> PIRQH
  31          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  32          */
  33
  34         /* Device interrupt pin register (board specific) */
  35         RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  36                 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  37         RCBA32(D30IP) = (NOINT << D30IP_PIP);
  38         RCBA32(D29IP) = (INTA << D29IP_E1P);
  39         RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
  40                 (INTB << D28IP_P4IP);
  41         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  42         RCBA32(D26IP) = (INTA << D26IP_E2P);
  43         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  44         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  45
  46         /* Device interrupt route registers */
  47         DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
  48         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
  49         DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
  50         DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
  51         DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
  52         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
  53         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
  54 }
  55
  56 static void setup_sio_gpios(void)
  57 {
  58         /*
  59          * GPIO10 as USBPWRON12#
  60          * GPIO12 as USBPWRON13#
  61          */
  62         ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(0), 0x05);
  63         ite_gpio_setup(GPIO_DEV, 10, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  64                        ITE_GPIO_POL_INVERT);
  65         ite_gpio_setup(GPIO_DEV, 12, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  66                        ITE_GPIO_POL_INVERT);
  67         /*
  68          * GPIO22 as wake SCI#
  69          */
  70         ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(1), 0x04);
  71         ite_gpio_setup(GPIO_DEV, 22, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  72                        ITE_GPIO_POL_INVERT);
  73         /*
  74          * GPIO32 as EXTSMI#
  75          */
  76         ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(2), 0x04);
  77         ite_gpio_setup(GPIO_DEV, 32, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  78                        ITE_GPIO_POL_INVERT);
  79         /*
  80          * GPIO45 as LED_POWER#
  81          */
  82         ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(3), 0x20);
  83         ite_gpio_setup(GPIO_DEV, 45, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  84                        ITE_GPIO_POL_INVERT | ITE_GPIO_PULLUP_ENABLE);
  85         ite_gpio_setup_led(GPIO_DEV, 45, ITE_GPIO_LED_1, ITE_LED_FREQ_1HZ,
  86                            ITE_LED_CONTROL_DEFAULT);
  87         /*
  88          * GPIO51 as USBPWRON8#
  89          * GPIO52 as USBPWRON1#
  90          */
  91         ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(4), 0x06);
  92         ite_gpio_setup(GPIO_DEV, 51, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  93                        ITE_GPIO_POL_INVERT);
  94         ite_gpio_setup(GPIO_DEV, 52, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
  95                        ITE_GPIO_POL_INVERT);
  96 }
  97
  98 void mainboard_fill_pei_data(struct pei_data *pei_data)
  99 {
 100         /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 101 }
 102
 103 void bootblock_mainboard_early_init(void)
 104 {
 105         if (CONFIG(DRIVERS_UART_8250IO))
 106                 try_enabling_LPC47N207_uart();
 107
 108         setup_sio_gpios();
 109
 110         /* Early SuperIO setup */
 111         ite_ac_resume_southbridge(EC_DEV);
 112         ite_kill_watchdog(GPIO_DEV);
 113         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 114 }